Overview

The Cadence® 112G-XSR SerDes PHY IP is a high-performance, low-latency PHY for die-to-die (D2D) and die-to-optical engine (D2OE) connectivities. The 112G-XSR SerDes utilizes PAM4 signaling and is designed to support interoperability with 112G-LR/MR/VSR SerDes.

Key Benefits

Interoperability

Interoperable with 112G-LR/MR/VSR

Maximize beach front bandwidth

Delivers up to 1Tbps/mm unidirectional bandwidth

Layout flexibility

Can be used as NS or EW for placement in any die edge

Features

  • Supports PAM4 and NRZ modulations and multiple high-speed data rates including 106.25Gbps PAM4 and 53.125Gbps NRZ
  • Capable of equalizing up to 10dB insertion loss @ 28GHz, bump-to-bump
  • Low power CTLE receiver front-end, including on-die AC coupling capacitor
  • Continuous and adaptive transmitter/receiver equalization, including baud-rate CDR
  • Data path BIST with programmable pattern generation and error detection
  • Supports stuck-at scan, at-speed scan, MBIST, and AC-JTAG (boundary scan)

Resources

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