Overview

The 112G-ELR SerDes delivers exceptional extended long-reach performance with superior margin, optimized power and area that is ideal for the next-generation cloud networking, artificial intelligence and machine learning (AI/ML), and 5G wireless applications. The SerDes PHY IP supports PAM4 and NRZ signaling and data rates from 1G to 112G and incorporates industry-leading analog-to-digital converter (ADC), clock-data-recovery (CDR), and digital signal process (DSP) technology with maximum likelihood sequence detector (MLSD) that enables the support of up to 45dB channel.

Key Benefits

Production Quality

Large number of customer production tapeouts and SoC proof points

Robust Performance

ADC/DSP-based receiver architecture with MLSD and reflection cancellation techniques provides superior data recovery for lossy and reflective channels

Comprehensive Testability

Rich diagnostic toolkit for easy observation and debugging

Features

  • Supports full-duplex 1Gbps to 112Gbps data rates
  • Superior bit error rate (BER) performance across high-loss and reflective channels 
  • Compliant to IEEE 802.3ck and OIF standard electrical specifications
  • Supports flexible SoC floorplan and IP placement provides package substrate guideline/reference designs
  • Available in multiple advanced-process nodes including 7nm, 6nm, 5nm, and 4nm
  • 400G Ethernet PHY + controller subsystem proven in silicon
  • Up to 800G Ethernet subsystem delivery with Cadence High-Speed Ethernet Controllers
112g-pam4-serdes