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  • 技術產品
    • DESIGN EXCELLENCE
      • 數位設計流程
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • 客製IC/類比/RF設計
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Virtuoso RF Solution
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus IC Power Integrity Solution
          • RESOURCES
          • Flows
      • 系統設計與驗證
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Emulation
          • Formal and Static Verification
          • FPGA-Based Prototyping
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
          • Palladium Z1 Enterprise Emulation Platform
          • Protium X1 Enterprise Prototyping Platform
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • Interface IP
          • Denali Memory IP
          • Tensilica Processor IP
          • Analog IP
          • System / Peripherals IP
          • Verification IP
      • IC封裝設計與分析
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
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          • Electromagnetic Solutions
          • RF / Microwave Design
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        • FEATURED PRODUCTS
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          • Sigrity Advanced SI
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          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
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Sigrity Advanced SI

Accelerate signal integrity analysis for PCB and IC packaging designs

Backchannel Modeling- White Paper
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Key Benefits

  • Reduces cost and time by identifying potential reflection and crosstalk problems early
  • Supports leading-edge SI interfaces with statistical and time-and frequency-domain analysis of serial and parallel links from DC to >56GHz

To help you quickly implement general topologies and standard interfaces, Cadence® Sigrity™ Advanced SI technology performs automated die-to-die signal integrity (SI) analysis in multiple modes:

  • Source-synchronous for parallel buses
  • Serial links, with an emphasis on SerDes channels
  • Free-form general-purpose topology exploration environment for signal, power, or combined what-if analysis

Covering the range DC to over 56GHz (112Gbps), our Advanced SI technology uses frequency domain, time domain, and statistical analysis methods.

Figure 1: The SystemSI topology environment

Sigrity Topology Explorer

This general-purpose topology exploration function is ideal for exploring end-to-end signal and power topologies, including letting you perform SI or transient power integrity (PI) analysis together. Also, you can include complex interconnect models and connect them to a single driver/receiver/discreet symbol that automatically replicates the circuit for each of the ports on the interconnect model. This functionality is included with Sigrity Aurora, where nets can be automatically extracted from a physical PCB or IC package design.

Sigrity SystemSI Parallel Bus Analysis

This end-to-end analysis targets source-synchronous parallel interfaces such as designs with DDRx memory. Pre-layout capabilities (including a via wizard) enable you to begin with models that are quickly generated and connected. As the design is refined, you can swap in more detailed models to reflect actual hardware design. Advanced SI includes the ability to:

  • Create interconnect models for reflection analysis and crosstalk analysis
  • Perform simultaneous switching noise (SSN) analysis, using finite-difference time-domain direct (FDTD-direct) that supports accurate SSN analysis without the use of S-parameters (you can import S-parameters using tools such as those included in Cadence Extraction Suites)
  • Create SPICE models from S-parameters with Cadence Sigrity Broadband SPICE® utility, part of the Advanced SI technology
  • Add equalization effects in both the read and write transmissions. IBIS-AMI models may be added, and channel simulation can be applied to run million-bit simulations to perform bit error rate (BER) simulations

The concurrent simulation accounts for the effects of dielectric and conductor losses, reflections, inter-symbol interference (ISI), crosstalk, and SSN. These simulations can fully account for the effects of non-ideal power-delivery systems. Graphical outputs and post-processing options give insight for rapid system improvements.

Simulation results can be compared against common JEDEC standard requirements, such as DDR4 and DDR5, to ensure that the design meets the standard compliance requirements. If desired, additional tests can be configured to augment a compliance test or create a custom compliance kit for proprietary IP.

Sigrity SystemSI Serial Link Analysis

Make early assessments using basic templates with this award-winning chip-to-chip analysis that focuses on high-speed SerDes designs such as PCI Express® (PCIe®), HDMI, SFP+, Xaui, Infiniband, SAS, SATA, and USB. Industry-standard IBIS-AMI transmitter and receiver model support lets you perform simulations of channel behavior for serial links with chips from multiple suppliers. If you’re a chip model developer, you have access to techniques that assist in IBIS-AMI model development. You can add models of multiple packages, connectors, and boards to reflect the entire channel. Simulations identify crosstalk issues and show the effectiveness of chip-level clock and data recovery (CDR) techniques. Full-channel simulations, including millions of bits of data, confirm overall BER to determine if jitter and noise levels are within specified tolerances. You can get compliance kits for popular interfaces (i.e., PCIe 5.0) to automate the required signal quality checks. You can also configure a custom compliance kit if it is not available for your preferred standard.

Figure 2: The intuitive SystemSI user experience makes it easy to join coupled
interconnect models through signal, power, and ground port connectivity

Features

  • Accurate handling of non-ideal power delivery system influences on SI
  • Concurrently evaluate SI effects such as losses, reflections, crosstalk, and simultaneous switching output (SSO)
  • Support for industry-standard IBIS-AMI transmitter and receiver models enables simulations of channel behavior for serial links with chips from multiple suppliers
  • Highly automated measurement and reporting capabilities

Contact Us

Learn how Avera Semi, acquired by Marvell, improved signal analysis for their LPDDR4 interfaces on MCM packages using Cadence Sigrity tools.

  • Related Products

    • Sigrity System Explorer
    • Sigrity SPEED2000
    • Sigrity SystemSI
    • Sigrity Broadband SPICE
Videos

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Seagate Uses Cadence Allegro and Sigrity PCB Tools to Develop Next-Generation Solid-State Drives

DesignCon 2017: Sigrity 2017 Portfolio Highlights

Sigrity Tech Tip: How to Build an IBIS-AMI Model

Sigrity Tech Tip: How DDR interfaces can be accurately analyzed pain-free (without large S-parameters)

Why Does Signal Integrity Analysis Need to be Power-Aware?

Simulation of the Automotive Ethernet using Cadence Sigrity tools

Ericsson Meets DDR and PCIe Specs While Avoiding Crosstalk

News ReleasesVIEW ALL
  • Cadence 3D-IC Advanced Packaging Integration Flow Certified by Samsung Foundry for its 7LPP Process Technology 10/17/2019

  • Cadence Design Solutions Certified for TSMC-SoIC Advanced 3D Chip Stacking Technology 04/23/2019

  • Cadence Sigrity 2018 Release Accelerates PCB Design Cycles by Integrating 3D Design and 3D Analysis 07/19/2018

  • Cadence Supports New TSMC WoW Advanced Packaging Technology 05/01/2018

  • Cadence Sigrity PowerDC Technology Supports Future Facilities' New Open Neutral File Format for Thermal Interoperability 03/19/2018

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