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  • 技術產品
    • DESIGN EXCELLENCE
      • 數位設計流程
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
          • Voltus IC Power Integrity Solution
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          • Spectre X Simulator
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          • Virtuoso Layout Suite
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          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • 系統設計與驗證
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
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          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
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          • Helium Virtual and Hybrid Studio
      • IP
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        • RESOURCES
          • Discover PCIe
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Sigrity SystemSI

Quickly implement general topologies and standard interfaces

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Key Benefits

  • Reduces cost and time by identifying potential problems early
  • Statistical and time- and frequency-domain analysis of serial and parallel links from DC to >56GHz
  • Simple block-based schematic editor to get started, supported by related Cadence tools

To help you quickly implement general topologies and standard interfaces, Cadence® Sigrity™ SystemSI™ technology performs automated die-to-die signal integrity analysis in two configurations: source-synchronous for parallel buses and serial links, with an emphasis on SerDes channels. Covering the range DC to over 56GHz, the SystemSI technology uses frequency domain, time domain, and statistical analysis methods. Both configurations are augmented with a general-purpose topology exploration tool.

Sigrity SystemSI brings three major features to bear to accelerate the design of your next interface.

Sigrity System Explorer

This general-purpose topology exploration tool is perfect for exploring end-to-end signal and power topologies, including letting you perform signal-integrity or transient power-integrity analysis together. Also, you can include complex interconnect models and connect them to a single driver/receiver/discreet symbol that automatically replicates the circuit for each of the ports on the interconnect model.

Sigrity SystemSI Parallel Bus Analysis

This end-to-end analysis solution targets source-synchronous parallel interfaces such as designs with DDRx memory. Pre-layout capabilities (including a via wizard) enable you to begin with models that are quickly generated and connected. As the design is refined, more detailed models can be swapped in to reflect actual hardware behavior. Concurrent simulation accounts for the effects of dielectric and conductor losses, reflections, inter-symbol interference (ISI), crosstalk, and simultaneous switching noise. These simulations are able to fully account for the effects of non-ideal power-delivery systems. Graphical outputs and post-processing options give insight for rapid system improvements.

Sigrity SystemSI Serial Link Analysis

This award-winning chip-to-chip analysis solution focuses on your high-speed SerDes designs, such as PCI Express® (PCIe®), HDMI, SFP+, Xaui, Infiniband, SAS, SATA, and USB, and makes early assessments using basic templates. Support for industry-standard IBIS AMI transmitter and receiver models let you perform simulations of channel behavior for serial links with chips from multiple suppliers. If you’re a chip model developer, you have access to techniques that assist in IBIS-AMI model development. You can add models of multiple packages, connectors, and boards to reflect the entire channel. Simulations identify crosstalk issues and show the effectiveness of chip-level clock and data recovery (CDR) techniques. Full-channel simulations including millions of bits of data confirm overall bit-error rate (BER) to determine if jitter and noise levels are within specified tolerances.

 

Screenshot shows how Sigrity SystemSI starts with a block-based schematic editor to make it easy to get started with very basic data


To help ease you into the environment, Sigrity SystemSI starts with a block-based schematic editor to make it easy to get started with very basic data. As design work progresses, models are swapped in to reflect the detail of design structures.

Features

  • Accurate handling of non-ideal power delivery system influences on SI
  • Concurrently evaluate SI effects such as losses, reflections, crosstalk, and simultaneous switching output (SSO)
  • Support for industry-standard IBIS AMI transmitter and receiver models enable simulations of channel behavior for serial links with chips from multiple suppliers
  • Highly automated measurement and reporting capabilities

Contact Us

Learn how Avera Semi, a subsidiary of GLOBALFOUNDRIES, improved signal analysis for their LPDDR4 interfaces on MCM packages using Cadence Sigrity tools.

  • Related Information

    • Top 10 Reasons Real Signal Integrity Engineers Demand Power-Aware SI Technology
  • Related Products

    • Sigrity SPEED2000
    • Sigrity PowerSI
    • Clarity 3D Solver
    • Sigrity Advanced SI
Resource Library

Conference Paper (10)

  • IBIS-AMI and Statistical Analysis Conference Presentation
  • Baseband IC Design Kits for Rapid System Realization
  • Accurate Modelling of PCIe 3.0 Analog Buffers Conference Paper
  • Bridging the Measurement and Simulation Gap Conference Paper
  • Model Extraction and Circuit Simulation Approaches for Successful SSO Analysis of Chip-Package-Board Systems Conference Paper
  • The Application of IBIS-AMI Model Cascaded Simulation for 10 Gigabit Repeater Serial Link Analysis Conference Presentation
  • AMI Simulation with Error Correction to Enhance BER Conference Paper
  • AMI Simulation with Error Correction to Enhance BER Performance Conference Presentation
  • IBIS–AMI Modeling Recommendations Conference Presentation
  • Panel Session TP-TU3 High-speed Channel Designs IBIS AMI Solution Conference Presentation

Presentation (4)

  • Using Automated IBIS AMI Modeling Tools to Model Advanced SerDes IP Presentation
  • Learn How to Turn Simulation into Reality for PAM4 Analysis Presentation
  • How to Efficiently Analyze a DDR4 Interface
  • Model Extraction and Circuit Simulation Approaches for Successful SSO Analysis of Chip-Package-Board Systems Presentation

Technical Brief (2)

  • Addressing the “Power-Aware” Challenges of Memory Interface Designs Technical Paper
  • Addressing the “Power-Aware” Challenges of Memory Interface Designs Technical Paper - Chinese version

Press Releases (9)

  • Cadence 3D-IC Advanced Packaging Integration Flow Certified by Samsung Foundry for its 7LPP Process Technology | Cadence
  • Cadence Design Solutions Certified for TSMC-SoIC Advanced 3D Chip Stacking Technology | Cadence
  • Cadence Sigrity 2018 Release Accelerates PCB Design Cycles by Integrating 3D Design and 3D Analysis | Cadence
  • Cadence Supports New TSMC WoW Advanced Packaging Technology | Cadence
  • Cadence Sigrity PowerDC Technology Supports Future Facilities' New Open Neutral File Format for Thermal Interoperability | Cadence
  • Cadence Sigrity 2017 Delivers Fast Path to PCB Power Integrity Signoff | Cadence
  • Cadence Sigrity 2016 Portfolio Improves Product Creation Time with PCB Design and Analysis Methodology for Multi-Gigabit Interfaces | Cadence
  • Cadence and Spreadtrum Collaborate on Virtual Reference Design Kit to Reduce Customers' Design Cycle by Up to 12 Weeks | Cadence
  • Cadence Expands Sigrity 2015 Technology Portfolio with New Products, a Key Feature Update and Flexible Licensing Options | Cadence

White Paper (3)

  • Overcoming Signal, Power, and Thermal Challenges Implementing GDDR6 Interfaces
  • Power-Aware Analysis Solution Whitepaper

Article (1)

  • Signal Integrity
VIEW ALL
Videos

GLOBALFOUNDRIES: MCM LPDDR4 Analysis Accelerates Turnaround Time by 12X Using Sigrity SystemSI

Cadence Solves the Challenges Faced by Mobiveil Technologies Hardware Group

Seagate Uses Cadence Allegro and Sigrity PCB Tools to Develop Next-Generation Solid-State Drives

DesignCon 2017: Sigrity 2017 Portfolio Highlights

Sigrity Tech Tip: How to Build an IBIS-AMI Model

Sigrity Tech Tip: How DDR interfaces can be accurately analyzed pain-free (without large S-parameters)

Why Does Signal Integrity Analysis Need to be Power-Aware?

Simulation of the Automotive Ethernet using Cadence Sigrity tools

Ericsson Meets DDR and PCIe Specs While Avoiding Crosstalk

News ReleasesVIEW ALL
  • Cadence 3D-IC Advanced Packaging Integration Flow Certified by Samsung Foundry for its 7LPP Process Technology 10/17/2019

  • Cadence Design Solutions Certified for TSMC-SoIC Advanced 3D Chip Stacking Technology 04/23/2019

  • Cadence Sigrity 2018 Release Accelerates PCB Design Cycles by Integrating 3D Design and 3D Analysis 07/19/2018

  • Cadence Supports New TSMC WoW Advanced Packaging Technology 05/01/2018

  • Cadence Sigrity PowerDC Technology Supports Future Facilities' New Open Neutral File Format for Thermal Interoperability 03/19/2018

Blogs VIEW ALL
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