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Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

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  • 技術產品
    • DESIGN EXCELLENCE
      • 數位設計流程
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
          • Voltus IC Power Integrity Solution
      • 客製IC/類比/RF設計
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • 系統設計與驗證
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
      • IP
        • PRODUCT CATEGORIES
          • Denali Memory Interface and Storage IP
          • 112G/56G SerDes
          • PCIe and CXL
          • Tensilica Processor IP
          • Chiplet and D2D
          • Interface IP
        • RESOURCES
          • Discover PCIe
      • IC封裝設計與分析
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
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      • 嵌入式軟體
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        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
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Sigrity OptimizePI

Optimize implementations for performance and cost

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Key Benefits

  • Automates selection and placement of decoupling capacitors
  • Ensures power-delivery system needs are met, at lowest decap costs
  • Recaptures usable design area used by unnecessary decaps

To ensure you get high performance at a system and component level, while at the same time saving between 15% and 50% in decoupling capacitor (decap) costs, Cadence® Sigrity™ OptimizePI™ technology does a complete AC frequency analysis of boards and IC packages. Supporting both pre- and post-layout studies, it quickly pinpoints the best decap selections and placement locations to meet your power-delivery network (PDN) needs at the lowest possible cost.

Sigrity OptimizePI technology is built on proven Cadence hybrid electromagnetic circuit analysis technology in combination with the unique Sigrity optimization engine to help you quickly pinpoint the best possible decap selections and placement locations.

 

Image showing the Cadence Sigrity OptimizePI interface

Features

  • Eliminates decap over-design for PCBs and IC packages
  • Reduces PDN cost for new designs and post-production products
  • Develops effective decap guidelines for packaged components
  • Optimizes a PDN across the board/package interface
  • Identifies both the number and locations for EMI decaps
  • Robust and proven underlying hybrid EM/circuit analysis technology
  • Intuitive and interactive visualization of PDN performance
  • Simple to set up for pre- and post-layout decap optimization
  • Visualize the power portion of your schematics with Cadence Allegro® PowerTree™ data
  • Capture setup information (models, net names, etc.) in a PowerTree GUI that enables assignment of target impedence constraints
  • Unique device impedance and EMI resonance checking
  • Ability to support large designs that include both package and board data
  • Optimized for flows with Cadence SiP Layout, Allegro Package Designer, and Allegro PCB Designer
  • Readily used in Mentor, Zuken, and Altium flows, accepting a mix of CAD databases where needed for multi-structure design support

Contact Us

View a demo of Sigrity OptimizePI which provides an analytical basis for decisions regarding PDN design tradeoffs.

  • Related Products

    • Celsius Advanced PTI
    • Sigrity Aurora
    • Celsius DC
    • Sigrity PowerSI
Resource Library

Press Releases (6)

  • Cadence Sigrity 2018 Release Accelerates PCB Design Cycles by Integrating 3D Design and 3D Analysis | Cadence
  • Cadence Sigrity PowerDC Technology Supports Future Facilities' New Open Neutral File Format for Thermal Interoperability | Cadence
  • Cadence Sigrity 2017 Delivers Fast Path to PCB Power Integrity Signoff | Cadence
  • Cadence Sigrity 2016 Portfolio Improves Product Creation Time with PCB Design and Analysis Methodology for Multi-Gigabit Interfaces | Cadence
  • Cadence and Spreadtrum Collaborate on Virtual Reference Design Kit to Reduce Customers' Design Cycle by Up to 12 Weeks | Cadence
  • Cadence Expands Sigrity 2015 Technology Portfolio with New Products, a Key Feature Update and Flexible Licensing Options | Cadence

Article (1)

  • A New Power Delivery System Design Practice

Conference Paper (2)

  • Power Integrity Conference Paper
  • Power Integrity in System Design Conference Paper

Presentation (1)

  • CAE Flow in the Development for the Digital Equipments Conference Presentation
VIEW ALL
News ReleasesVIEW ALL
  • Cadence Sigrity 2018 Release Accelerates PCB Design Cycles by Integrating 3D Design and 3D Analysis 07/19/2018

  • Cadence Sigrity PowerDC Technology Supports Future Facilities' New Open Neutral File Format for Thermal Interoperability 03/19/2018

  • Cadence Sigrity 2017 Delivers Fast Path to PCB Power Integrity Signoff 01/25/2017

  • Cadence Sigrity 2016 Portfolio Improves Product Creation Time with PCB Design and Analysis Methodology for Multi-Gigabit Interfaces 01/19/2016

  • Cadence and Spreadtrum Collaborate on Virtual Reference Design Kit to Reduce Customers' Design Cycle by Up to 12 Weeks 12/01/2015

Blogs VIEW ALL
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