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數位設計流程

Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

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客製IC/類比/RF設計

Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

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系統設計與驗證

Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.

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An open IP platform for you to customize your app-driven SoC design.

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Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.

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Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

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  • 技術產品
    • DESIGN EXCELLENCE
      • 數位設計流程
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • 客製IC/類比/RF設計
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Virtuoso RF Solution
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus IC Power Integrity Solution
          • RESOURCES
          • Flows
      • 系統設計與驗證
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Emulation
          • Formal and Static Verification
          • FPGA-Based Prototyping
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
          • Palladium Z1 Enterprise Emulation Platform
          • Protium X1 Enterprise Prototyping Platform
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • Interface IP
          • Denali Memory IP
          • Tensilica Processor IP
          • Analog IP
          • System / Peripherals IP
          • Verification IP
      • IC封裝設計與分析
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • 系統分析
        • PRODUCT CATEGORIES
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Sigrity Advanced SI
          • Sigrity Advanced PI
          • RESOURCES
          • System Analysis Resources Hub
      • 嵌入式軟體
      • PCB設計與分析
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • What's New in Sigrity
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
    • PERVASIVE INTELLIGENCE
      • AI / 機器學習
      • AI IP系列
    • CADENCE雲端方案
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        • 先進製程
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        • Photonics
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      • Industries
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        • 車用方案
        • AI / 機器學習
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        • 先進製程
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        • 低功耗方案
        • 混合訊號
        • Photonics
        • RF / Microwave
      • Industries
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        • 車用方案
        • AI / 機器學習
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        • 先進製程
        • Arm-Based方案
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Allegro Package Designer Plus

Powerful physical package implementation

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Key Benefits

  • Full front-to-back physical design implementation flow for single- and multi-die wire bond, flip-chip, and wafer-level chip-scale packaging, silicon interposer, die stacking, and other advanced packaging technologies
  • Efficient and chip IP-secure distributed co-design for chip/package optimization
  • Constraint-driven substrate interconnect design, extraction, modeling, and signal integrity analysis

Cadence® Allegro® Package Designer Plus enables constraint-driven, correct-by-design package substrate layout. It supports a full front-to-back physical implementation flow for single- and multi-die BGA/LGA package design. A robust set of packaging-specific features are available, such as on-the-fly library development, connectivity generation/optimization, multi-tiered wire-bonding, co-design, die stacking and TSVs, embedded cavities, push/shove routing, reports, and manufacturing outputs. 

Allegro Package Designer Plus UI

System Design Integration

Truly integrated with Cadence OrbitIO™ system planning, Allegro Package Designer Plus offers complete package implementation capabilities to help you make strategic tradeoffs earlier and with greater confidence.

The tool also provides direct interfaces with Cadence Sigrity™, Clarity™, and Celsius™ analysis technologies, providing an integrated layout and analysis flow that supports virtually all advanced IC packaging technologies such as complex wire bond, copper pillar, FOWLP, 2.5D, 3D, BGA, and PoP.

Key Features

  • Optimized physical layout solution for single- and multi-die packages with a correct-by-construction database, real-time DRC of physical design rules and electrical constraints
  • Constraint-driven push-and-shove interactive routing, auto-interactives, and full auto-routing
  • Flexible connectivity model, supporting netlist, schematic, and “on-the-fly” connectivity
  • Includes core DesignTrue DFM rule checking
  • Visualize and perform 3D wire and design rule checks
Allegro Package Designer Plus 3D Canvas

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  • Related Products

    • Allegro Package Designer Plus SiP Layout Option
    • Allegro Package Designer Plus Silicon Layout Option
    • OrbitIO Interconnect Designer
    • Clarity 3D Solver
    • Celsius Thermal Solver
    • Allegro PCB Symphony Team Design Option for IC Packaging
News ReleasesVIEW ALL
  • Cadence 3D-IC Advanced Packaging Integration Flow Certified by Samsung Foundry for its 7LPP Process Technology 10/17/2019

  • Cadence Design Solutions Certified for TSMC-SoIC Advanced 3D Chip Stacking Technology 04/23/2019

  • Cadence Delivers Support for TSMC InFO_MS Advanced Packaging Technologies 10/02/2018

  • Cadence Supports New TSMC WoW Advanced Packaging Technology 05/01/2018

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