Concerned about your test costs? Reduce your SoC test time by up to 3X with the Cadence® Modus DFT Software Solution. Introducing a new patented 2D Elastic Compression architecture, this next-generation tool enables compression ratios beyond 400X without impacting design size or routing. With a complete suite of industry-standard capabilities for memory BIST, logic BIST, test point insertion, and diagnostics, the solution can help you reduce your production test costs and increase silicon profit margins.
Key Features
The 2D Elastic Compression architecture in the Cadence Modus DFT Software Solution consists of:
- Modus 2D Compression: XOR compression logic forms a physically aware 2D grid across the design floorplan, enabling higher compression ratios with reduced wirelength. At 100X compression ratios, wirelength for 2D compression can be up to 2.6X smaller than current industry scan compression architectures.
- Modus Elastic Compression: Registers embedded in the decompression logic enable fault coverage to be maintained at compression ratios beyond 400X by controlling care bits sequentially across multiple scan cycles during ATPG. Extends to LBIST and MISR compression.
- Flexible DFT insertion: Integration with synthesis and implementation flows or standalone. All Cadence Modus DFT logic insertion is natively integrated within the Genus™ Synthesis Solution cockpit, or available as a standalone netlist-based solution for use with third-party synthesis. The solution’s Modus ATPG component also shares a common Tcl scripting and debug language with the Genus Synthesis Solution, the Innovus™ Implementation System, and the Tempus™ Timing Signoff Solution, streamlining flow development and simplifying user training across a complete Cadence digital flow.
What’s in the Solution?
In addition to Modus 2D Elastic Compression, the Cadence Modus DFT Software Solution encompasses:
- Modus DFT: Natively integrated with the Genus Synthesis Solution or standalone, inserts full-chip test logic including full scan, boundary scan, compression, low pin count architecture, X-masking, on-chip clock controller, JTAG controller, IEEE 1687 (iJTAG), and IEEE 1500. Power aware, leveraging the same UPF/CPF power intent file used for implementation. SDC constraints for test modes and Modus ATPG run scripts are automatically generated for further ease of use.
- Modus ATPG: Static and delay fault test pattern generation, low-power test pattern generation with scan and capture toggle count limits, and distributed test pattern generation with near-linear runtime scalability across multiple machines and CPUs. Flexible and robust X-masking. Standalone or integrated test point analysis and insertion.
- Modus Diagnostics: Single- and multi-die volume diagnostics, with physical defect location callout and root-cause analysis for logic gates and memories. Simulates multiple defect types concurrently, reorders compressed/uncompressed patterns. Support for advanced fault models, including cell aware.
- Modus Programmable Memory BIST Option: RTL or netlist level insertion and support for soft and hard repair. Embedded memory bus support integrates seamlessly with macro interface for at-speed PMBIST across multiple embedded memories in an IP core and support for Arm® MBIST interface. New programmable test algorithms for FinFET SRAMs and automotive safety applications.
- Modus Logic BIST Option: Production proven in ASIL-D designs. Support for JTAG or direct access. Integrates with 2D Elastic Compression for ease of routability.
