The Cadence® CerebrusTM Intelligent Chip Explorer is a revolutionary, machine learning-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and Cerebrus will intelligently optimize the Cadence digital full flow to meet these power, performance, and area (PPA) goals in a completely automated way. By adopting Cerebrus, it is possible for engineers to concurrently optimize the flow for multiple blocks, which is especially important for the large, complex system-on-chip (SoC) designs needed for today’s ever more powerful electronic systems. Additionally, through the Cerebrus full flow reinforcement learning technology, engineering team productivity is greatly improved.
Chip design flow from RTL to GDS, automatically optimized for PPA
Engineers can quickly optimize flows for many blocks concurrently and use that knowledge for the next design
Efficient distributed compute machine learning technology, also enabled for cloud
Easy to Use
Designer cockpit allows interactive results analysis, so engineers always have control
Machine learning-driven, automated approach to digital chip design
Using machine learning to automate chip design from RTL to GDS for full flow optimization provides PPA and Productivity...
Cerebrus Automated ML Chip Design Technology Overview
Venkat Thanvantri, VP of Machine Learning R&D, describes the innovative distributed computing and reinforcement learning...
Cadence Extends Digital Design Leadership with ML-based Cerebrus
Cadence announced the delivery of the Cadence Cerebrus Intelligent Chip Explorer, a new ML-based tool that automates and scales digital chip design, enabling customers to efficiently achieve demanding chip design goals.