Tempus Timing Signoff Solution

The Cadence^® Tempus^™ Timing Signoff Solution is the industry’s most trusted static timing analysis (STA) tool for FinFET designs. It is the fastest STA tool in the industry today with unique distributed processing and cloud capabilities scaling to hundreds of CPUs to quickly complete even the largest designs.

With full foundry certification and a comprehensive set of advanced capabilities, the cloud-ready Tempus solution delivers SPICE-accurate results to hundreds of customers across a broad range of design types: from the high-performance designs to high-volume mobile designs, and mixed-signal chips on mature processes.

The Tempus solution is designed to tackle the most advanced timing requirements including full signal integrity (SI) analysis, glitch analysis and propagation, statistical on-chip variation (SOCV), multi-mode and multi-corner (MMMC) analysis, static and dynamic power reduction, and hierarchical timing models.

More than just an analysis tool, the Tempus solution is also deeply integrated with the Cadence Innovus^™ Implementation System, Quantus^™ Extraction Solution, and Voltus^™ IC Power Solution.

Tempus Power Integrity Integration with Voltus Solution for STA-Aware IR Drop

Traditional IR drop methodologies have struggled to keep up with the latest silicon technologies, leading to an increase in silicon failures at 7nm and below. The Tempus Power Integrity option integrates the Tempus and Voltus solutions to deliver next-generation IR drop analysis and fixing technology.

Tempus Power Integrity identifies voltage-sensitive paths in your design and then automatically generates activity vectors that will activate these voltage-sensitive paths as well as nearby voltage aggressor cells, thereby finding potential IR drop failures that traditional methodologies miss. Once detected, Tempus ECO will automatically fix IR drop issues by optimizing both the victim and aggressor paths.