Home
  • 技術產品
  • 解決方案
  • 支援與培訓
  • 公司資訊
  • ZH TW
    • SELECT YOUR COUNTRY OR REGION

    • US - English
    • China - 简体中文
    • Japan - 日本語
    • Korea - 한국어

DESIGN EXCELLENCE

  • 數位設計流程
  • 客製IC/類比/RF設計
  • Verification
  • IP
  • IC封裝設計與分析

SYSTEM INNOVATION

  • 系統分析
  • 嵌入式軟體
  • PCB設計與分析

PERVASIVE INTELLIGENCE

  • AI / 機器學習
  • AI IP系列

CADENCE雲端方案

VIEW ALL PRODUCTS

數位設計流程

Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

PRODUCT CATEGORIES

  • Logic Equivalence Checking
  • SoC Implementation and Floorplanning
  • Functional ECO
  • Low-Power Validation
  • Synthesis
  • Power Analysis
  • Constraints and CDC Signoff
  • Silicon Signoff and Verification
  • Library Characterization
  • Test

FEATURED PRODUCTS

  • Genus Synthesis Solution
  • Conformal Smart LEC
  • Innovus Implementation System
  • Tempus Timing Signoff Solution
  • Pegasus Verification System
  • RESOURCES
  • Flows

客製IC/類比/RF設計

Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

PRODUCT CATEGORIES

  • Circuit Design
  • Circuit Simulation
  • Layout Design
  • Layout Verification
  • Library Characterization
  • RF / Microwave Solutions

FEATURED PRODUCTS

  • Spectre X Simulator
  • Virtuoso RF Solution
  • Virtuoso Layout Suite
  • Virtuoso ADE Product Suite
  • Virtuoso Advanced Node
  • Voltus IC Power Integrity Solution
  • RESOURCES
  • Flows

系統設計與驗證

Offering a full verification flow to our customers and partners that delivers the highest verification throughput in the industry

PRODUCT CATEGORIES

  • Debug Analysis
  • Emulation and Prototyping
  • Formal and Static Verification
  • Planning and Management
  • Simulation
  • Software-Driven Verification
  • Verification IP
  • System-Level Verification IP

FEATURED PRODUCTS

  • vManager Verification Management
  • JasperGold Formal Verification Platform
  • Xcelium Logic Simulation
  • Palladium Enterprise Emulation
  • Protium Enterprise Prototyping
  • System VIP
  • RESOURCES
  • Flows

IP

An open IP platform for you to customize your app-driven SoC design.

PRODUCT CATEGORIES

  • Interface IP
  • Denali Memory IP
  • Tensilica Processor IP
  • Analog IP
  • System / Peripherals IP
  • Verification IP

IC封裝設計與分析

Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.

PRODUCT CATEGORIES

  • Cross-Platform Co-Design and Analysis
  • IC Package Design
  • SI/PI Analysis
  • SI/PI Analysis Point Tools
  • Flows

系統分析

Cadence® system analysis solutions provide highly accurate electromagnetic extraction and simulation analysis to ensure your system works under wide-ranging operating conditions.

PRODUCT CATEGORIES

  • Computational Fluid Dynamics
  • Electromagnetic Solutions
  • RF / Microwave Design
  • Signal and Power Integrity
  • Thermal Solutions

FEATURED PRODUCTS

  • Clarity 3D Solver
  • Clarity 3D Transient Solver
  • Celsius Thermal Solver
  • Omnis
  • Sigrity Advanced SI
  • Sigrity Advanced PI
  • RESOURCES
  • System Analysis Resources Hub
  • AWR Software Download Free Trial

嵌入式軟體

PCB設計與分析

Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

PRODUCT CATEGORIES

  • Design Authoring
  • PCB Layout
  • Library and Design Data Management
  • Analog/Mixed-Signal Simulation
  • SI/PI Analysis
  • SI/PI Analysis Point Tools
  • RF / Microwave Design
  • Augmented Reality Lab Tools

FEATURED PRODUCTS

  • Allegro Package Designer Plus
  • Allegro PCB Designer
  • RESOURCES
  • What's New in Allegro
  • What's New in Sigrity
  • Advanced PCB Design & Analysis Resources Hub
  • Flows

AI / 機器學習

AI IP系列

Industries

  • 5G 系統
  • 航太與國防
  • 車用方案
  • AI / 機器學習

Technologies

  • 3D-IC 設計
  • 先進製程
  • Arm-Based方案
  • Cloud Solutions
  • 低功耗方案
  • 混合訊號
  • Photonics
  • RF / Microwave
See how our customers create innovative products with Cadence

Support

  • Support Process
  • Online Support
  • Software Downloads
  • Computing Platform Support
  • Customer Support Contacts
  • Technical Forums

Training

  • Custom IC / Analog / RF Design
  • Languages and Methodologies
  • Digital Design and Signoff
  • IC Package
  • PCB Design
  • System Design and Verification
  • Tensilica Processor IP
Stay up to date with the latest software 24/7 - Cadence Online Support Visit Now

Corporate

  • About Us
  • Designed with Cadence
  • Investor Relations
  • Leadership Team
  • Computational Software
  • Alliances
  • Corporate Social Responsibility
  • Cadence Academic Network

Media Center

  • Events
  • Newsroom
  • Blogs

Culture and Careers

  • Culture and Diversity
  • Careers
Learn how Intelligent System Design™ powers future technologies Browse Cadence’s latest on-demand sessions and upcoming events. Explore More
ZH - Taiwan
  • US - English
  • China - 简体中文
  • Japan - 日本語
  • Korea - 한국어
  • 技術產品
    • DESIGN EXCELLENCE
      • 數位設計流程
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • 客製IC/類比/RF設計
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Virtuoso RF Solution
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus IC Power Integrity Solution
          • RESOURCES
          • Flows
      • 系統設計與驗證
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Emulation and Prototyping
          • Formal and Static Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • Interface IP
          • Denali Memory IP
          • Tensilica Processor IP
          • Analog IP
          • System / Peripherals IP
          • Verification IP
      • IC封裝設計與分析
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • 系統分析
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Omnis
          • Sigrity Advanced SI
          • Sigrity Advanced PI
          • RESOURCES
          • System Analysis Resources Hub
          • AWR Software Download Free Trial
      • 嵌入式軟體
      • PCB設計與分析
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • What's New in Sigrity
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
    • PERVASIVE INTELLIGENCE
      • AI / 機器學習
      • AI IP系列
    • CADENCE雲端方案
    • VIEW ALL PRODUCTS
  • 解決方案
      • Industries
        • 5G 系統
        • 航太與國防
        • 車用方案
        • AI / 機器學習
      • Technologies
        • 3D-IC 設計
        • 先進製程
        • Arm-Based方案
        • Cloud Solutions
        • 低功耗方案
        • 混合訊號
        • Photonics
        • RF / Microwave
      • Industries
        • 5G 系統
        • 航太與國防
        • 車用方案
        • AI / 機器學習
      • Technologies
        • 3D-IC 設計
        • 先進製程
        • Arm-Based方案
        • Cloud Solutions
        • 低功耗方案
        • 混合訊號
        • Photonics
        • RF / Microwave
      • Industries
        • 5G 系統
        • 航太與國防
        • 車用方案
        • AI / 機器學習
      • Technologies
        • 3D-IC 設計
        • 先進製程
        • Arm-Based方案
        • Cloud Solutions
        • 低功耗方案
        • 混合訊號
        • Photonics
        • RF / Microwave
  • 支援與培訓
      • Support
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • Training
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
      • Support
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • Training
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
      • Support
        • Support Process
        • Online Support
        • Software Downloads
        • Computing Platform Support
        • Customer Support Contacts
        • Technical Forums
      • Training
        • Custom IC / Analog / RF Design
        • Languages and Methodologies
        • Digital Design and Signoff
        • IC Package
        • PCB Design
        • System Design and Verification
        • Tensilica Processor IP
  • 公司資訊
      • Corporate
        • About Us
        • Designed with Cadence
        • Investor Relations
        • Leadership Team
        • Computational Software
        • Alliances
        • Corporate Social Responsibility
        • Cadence Academic Network
      • Media Center
        • Events
        • Newsroom
        • Blogs
      • Culture and Careers
        • Culture and Diversity
        • Careers
      • Corporate
        • About Us
        • Designed with Cadence
        • Investor Relations
        • Leadership Team
        • Computational Software
        • Alliances
        • Corporate Social Responsibility
        • Cadence Academic Network
      • Media Center
        • Events
        • Newsroom
        • Blogs
      • Culture and Careers
        • Culture and Diversity
        • Careers
      • Corporate
        • About Us
        • Designed with Cadence
        • Investor Relations
        • Leadership Team
        • Computational Software
        • Alliances
        • Corporate Social Responsibility
        • Cadence Academic Network
      • Media Center
        • Events
        • Newsroom
        • Blogs
      • Culture and Careers
        • Culture and Diversity
        • Careers

Tempus Timing Signoff Solution

Industry’s fastest-adopted and trusted timing signoff solution for FinFET designs

Read Datasheet Read White Paper
  • Overview
  • Videos
  • News and Blogs
  • Customers
  • Support and Training

Key Benefits

  • Achieve industry’s fastest runtimes on a single machine or in the cloud
  • Capacity to time over 1B instances flat with unique DSTA for full-chip signoff
  • Speed design closure time by 3X and save up to 5% dynamic power Tempus ECO tightly integrated with Innovus Implementation System for physically aware timing and power optimization
  • Find IR drop failures missed by traditional flows at 7nm and below with Tempus Power Integrity’s STA-aware IR drop analysis
  • ​Fully certified down to 3nm​
  • 5X faster runtime with CMMMC technology
  • Streamline flow development and simplify user trainings with new Common User Interface shared across the Cadence digital full flow
  • Accurate modeling of ultra-low voltage effects below 0.5V with advanced SI and SOCV; supports both Cadence SOCV library format and Liberty Variation Format (LVF)
  • Faster runtime and reduced memory with SmartScope hierarchical abstraction and boundary models providing the same accuracy as flat STA
  • Supports mixed-signal design through integration with Virtuoso Open Access database
ASK US A QUESTION

 

The Cadence® Tempus™ Timing Signoff Solution is the industry’s most trusted static timing analysis (STA) tool for FinFET designs. It is the fastest STA tool in the industry today with unique distributed processing and cloud capabilities scaling to hundreds of CPUs to quickly complete even the largest designs.

With full foundry certification and a comprehensive set of advanced capabilities, the cloud-ready Tempus solution delivers SPICE-accurate results to hundreds of customers across a broad range of design types: from the high-performance designs to high-volume mobile designs, and mixed-signal chips on mature processes.

The Tempus solution is designed to tackle the most advanced timing requirements including full signal integrity (SI) analysis, glitch analysis and propagation, statistical on-chip variation (SOCV), multi-mode and multi-corner (MMMC) analysis, static and dynamic power reduction, and hierarchical timing models.

More than just an analysis tool, the Tempus solution is also deeply integrated with the Cadence Innovus™ Implementation System, Quantus™ Extraction Solution, and Voltus™ IC Power Solution.

Tempus Power Integrity Integration with Voltus Solution for STA-Aware IR Drop

Traditional IR drop methodologies have struggled to keep up with the latest silicon technologies, leading to an increase in silicon failures at 7nm and below. The Tempus Power Integrity option integrates the Tempus and Voltus solutions to deliver next-generation IR drop analysis and fixing technology.

Tempus Power Integrity identifies voltage-sensitive paths in your design and then automatically generates activity vectors that will activate these voltage-sensitive paths as well as nearby voltage aggressor cells, thereby finding potential IR drop failures that traditional methodologies miss. Once detected, Tempus ECO will automatically fix IR drop issues by optimizing both the victim and aggressor paths.

Contact Us

TRAINING COURSES

Tempus Timing Signoff Solution Delivers 2X Faster Time-to-Signoff Closure

Blu Wireless Accelerates 5G mmWave Design Tapeout
LEARN MORE
Inphi Reduces Time to Market with 2X Turnaround Time Reduction
LEARN MORE
SiFive Tapeout FinFET Products Using Tempus ECO and Signoff
Learn More
Customers tapeout using Tempus ECO and Signoff with working silicon!
Read Article

Maxlinear通过在Innovus流程中使用Tempus 时序ECO和签核有效地降低了整体设计收敛时间,改善PPA

  • Related Products

    • Quantus Extraction Solution
    • Voltus IC Power Integrity Solution
    • Innovus Implementation System
    • Voltus-Fi Custom Power Integrity Solution
    • Virtuoso Layout Suite
  • Related Links

    • Mixed-Signal Implementation
    • Digital Advanced Node
    • Tempus Delivering Faster Timing Signoff with Optimal PPA
    • Cadence Defines a New Signoff Paradigm with Tempus PI
    • Barefoot Networks Accelerates Timing Closure with Cloudburst Platform and Tempus Timing Signoff
Videos

Tempus Power Integrity “True Signoff”

Maxlinear Signing-Off using Tempus with Confidence for FinFET Designs

Managing Signoff Corners with MMMC Flows

Mixed Signal STA Webinar

Getting What You’re Entitled to at 10nm by Reducing Timing Pessimism

Tempus Timing Signoff Solution Delivers 2X Faster Time-to-Signoff Closure

News ReleasesVIEW ALL
  • Cadence榮獲2020年四項台積電開放創新平台夥伴大獎 11/03/2020

  • GLOBALFOUNDRIES Collaborates with Cadence on Availability of Mixed-Signal OpenAccess PDK for 22FDX Platform to Enable Advanced Mixed-Signal and mmWave Design 09/24/2020

  • Cadence Digital and Custom Flows Achieve Certification for TSMC N3 Process 08/25/2020

  • Cadence Collaborates with TSMC and Microsoft to Reduce Semiconductor Design Timing Signoff Schedules with the Cloud 06/15/2020

  • Cadence Achieves Digital and Custom/Analog EDA Flow Certification for TSMC N6 and N5 Process Technologies 06/02/2020

Blogs VIEW ALL
Customers

The Tempus Timing Signoff Solution has been our timing tool for all of our SoCs that enable smart TV, set-top boxes and media connectivity. Its runtime performance, coupled with integration within the Cadence Innovus™ Implementation System, has allowed us to significantly reduce the time we spend in timing signoff.

Jacques Martinella, Vice President, Engineering, Sigma Designs

Read More or View All Customers

The size and complexity characteristics of our latest design required a timing solution that could handle more than 50M cells quickly and efficiently. We determined that the Tempus Timing Signoff Solution was the right timing platform to address our signoff analysis and closure needs.

Toru Hiyama, General Manager for Platform Advanced Engineering Operation, Information and Telecommunication System Company, Hitachi, Ltd.

Read More or View All Customers

The Tempus Timing Signoff Solution has enabled us to complete several successful tapeouts of our datacenter interconnect solutions. We were able to effectively use the tool for distributed multi-mode, multi-corner (MMMC) timing analysis and closure to get our products out the door and into the fab.

Lawrence Tse, Vice President of Engineering, Inphi

Read More or View All Customers

Support

Cadence is committed to keeping design teams highly productive. A range of support offerings and processes helps Cadence users focus on reducing time-to-market and achieving silicon success. Overview

Cadence Online Support

  • Details about online supportLearn more

  • Have an account already?Log in

  • New to support?Sign up

  • Online support overview Link to video

Customer Support

  • Support Process
  • Software Downloads
  • Computing Platform Support
  • University Software Program
  • Customer Support Contacts
Training

Get the most out of your investment in Cadence technologies through a wide range of training offerings. We offer instructor-led classes at our training centers or at your site. We also offer self-paced online courses. Overview

Course Delivery Methods

  • Instructor-Led Training
  • Online Training
  • Get Cadence Certified

Regional Training Information

  • China
  • Europe, Middle East, and Africa
  • India
  • Japan
  • Korea
  • North America
  • Singapore
  • Taiwan

A Great Place to Do Great Work!

Sixth year on the FORTUNE 100 list

Our Culture Join The Team
  • Products
  • Custom IC and RF
  • Digital Design and Signoff
  • IC Package
  • IP
  • PCB Design
  • System Analysis
  • Verification
  • All Products
  • Company
  • About Us
  • Leadership Team
  • Investor Relations
  • Alliances
  • Careers
  • Cadence Academic Network
  • Supplier
  • Media Center
  • Events
  • Newsroom
  • Press Releases
  • Designed with Cadence
  • Blogs
  • Forums
  • Contact Us
  • General Inquiry
  • Customer Support
  • Media Relations
  • Global Office Locator

Stay Connected

Please confirm to enroll for subscription!

Stay Connected

Thank you for subscribing. You will get an email to confirm your subscription.

© 2021 Cadence Design Systems, Inc. All Rights Reserved.

Terms of Use Privacy US Trademarks