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Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

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系統設計與驗證

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  • 技術產品
    • DESIGN EXCELLENCE
      • 數位設計流程
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
          • Voltus IC Power Integrity Solution
      • 客製IC/類比/RF設計
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • 系統設計與驗證
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
      • IP
        • PRODUCT CATEGORIES
          • Denali Memory Interface and Storage IP
          • 112G/56G SerDes
          • PCIe and CXL
          • Tensilica Processor IP
          • Chiplet and D2D
          • Interface IP
        • RESOURCES
          • Discover PCIe
      • IC封裝設計與分析
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
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        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • 嵌入式軟體
      • PCB設計與分析
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
      • Computational Fluid Dynamics
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Pegasus Verification System

Cloud-ready physical signoff solution

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Key Benefits

  • Flexible cloud-ready platform provides elastic and flexible compute environment
  • Massively parallel architecture provides unprecedented speed and capacity
  • Gigascale processing dramatically reduces full-chip physical verification runtimes
  • Near-linear scalability across 100s of CPUs enables predictable runtimes
  • Efficient use of CPU resources regardless of machine configuration and physical location
  • Low transition cost using existing foundry-certified rule decks
  • Native compatibility with Virtuoso® custom and the Innovus™ Implementation System platforms
ASK US A QUESTION

 

With the exponential increase in design rule check (DRC) complexity at advanced nodes, existing DRC solutions haven’t been able to support the turnaround requirements needed to ensure design schedules are met. Current DRC turnaround time takes several days using 64 CPUs, which is the optimal configuration for existing tools. Adding more CPUs does not improve the turnaround time because of the poor scalability of the current tools. At advanced nodes, DRC signoff cannot be run overnight, and even breaking up the deck and running sub-decks in parallel cannot meet the overnight runtime that critical projects need.

The Cadence® Pegasus™ Verification System is a cloud-ready physical verification signoff solution, which enables engineers to deliver advanced-node integrated circuits (ICs) to market faster. The groundbreaking technology delivers up to 10X improved performance on DRC runs and reduces turnaround time from days to hours. The Pegasus system’s innovative architecture and native cloud processing provides an elastic and flexible computing environment. Customers can now achieve complete full-chip signoff DRC on advanced-node designs in a matter of hours, helping designers deliver products to market faster, or easily run multiple DRC signoff iterations, if needed, at the time of tapeout.

Graph showing predictable DRC run times with near-linear scalability
Using the Pegasus system, jobs that previously ran for days can be completed in just a few hours, and offer predictable DRC run times with near-linear scalability

The Pegasus system provides a massively parallel architecture. It is the first solution to combine a pipelined infrastructure with stream processing delivering near-linear scalability across 100s of CPUs. The Pegasus system’s gigascale technology enables full-chip signoff DRC in just a few hours versus days. As many designs continue to grow in complexity, the Pegasus system can scale to meet customers’ stringent time-to-market requirements.

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The ENICS SoC Lab at Bar Ilan University tapedout the Israeli HiPer Consortium 16nm chip​ using Pegasus Verification System

The Pegasus Verification System lifts designs out of DRC bottlenecks with scalability, flexibility, and functionality for all kinds of flows.

  • Related Products

    • Pegasus Design Review Environment
    • Virtuoso Integrated Physical Verification System
    • Assura Physical Verification
    • Quantus Extraction Solution
    • Voltus-Fi Custom Power Integrity Solution
    • Virtuoso Layout Suite
    • Innovus Implementation System
Videos

Let Your DRC Fly with the Pegasus Verification System

Pegasus Verification System – Let Your DRC Fly!

Microsemi Benefits by Using Pegasus Verification System on Advanced-Node Designs

News ReleasesVIEW ALL
  • Cadence Expands Collaboration with TSMC and Microsoft to Accelerate Timing Signoff for Giga-Scale Designs on the Cloud 12/01/2021

  • Cadence Integrity 3D-IC Platform Qualified by Samsung Foundry for Native 3D Partitioning Flow on 5LPE Design Stack 11/17/2021

  • Samsung Foundry Adopts New Tempus SPICE-Accurate Aging Analysis for High-Reliability Applications 11/16/2021

  • Cadence Wins Four 2021 TSMC OIP Partner of the Year Awards, Featuring Key Advancements in 3DFabric Design and Cloud-Based Solutions 11/12/2021

  • Cadence Integrity 3D-IC Platform Supports TSMC 3DFabric™ Technologies for Advanced Multi-Chiplet Designs 10/26/2021

Blogs VIEW ALL
Customers

As technology nodes advance, Microsemi is leveraging the Cadence Pegasus Verification System to shorten our time to tapeout. Its near-linear scalability can enable us to scale full-chip DRC runs to hundreds of CPUs for short periods and achieve up to 10 times the speedup...

Scott Barrick, Senior Manager of Advanced Engineering Services, Microsemi Corporation

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