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數位設計流程

Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

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系統設計與驗證

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  • 技術產品
    • DESIGN EXCELLENCE
      • 數位設計流程
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
          • Voltus IC Power Integrity Solution
      • 客製IC/類比/RF設計
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-XFi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • 系統設計與驗證
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
      • IP
        • PRODUCT CATEGORIES
          • Denali Memory Interface and Storage IP
          • 112G/56G SerDes
          • PCIe and CXL
          • Tensilica Processor IP
          • Chiplet and D2D
          • Interface IP
        • RESOURCES
          • Discover PCIe
      • IC封裝設計與分析
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • 系統分析
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • 嵌入式軟體
      • PCB設計與分析
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
      • Computational Fluid Dynamics
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      • Industries
        • 5G 系統
        • 航太與國防
        • 車用方案
        • Hyperscale Computing
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        • 3D-IC 設計
        • 先進製程
        • AI / 機器學習
        • Arm-Based方案
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • 低功耗方案
        • 混合訊號
        • Photonics
        • RF / Microwave
      • Industries
        • 5G 系統
        • 航太與國防
        • 車用方案
        • Hyperscale Computing
      • Technologies
        • 3D-IC 設計
        • 先進製程
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Pegasus Computational Pattern Analytics

High-performance production-proven layout processing

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Key Benefits

  • In production use for 20+ years to process largest chip databases with unmatched performance
  • Fully enabled with data analytics and machine learning
  • Production-proven in the cloud with massive distribution and parallelization for faster throughput and linear scalability
  • Wide range of applications at both major foundries and fabless semiconductor companies
  • Versatile built-in and customizable applications

Cadence® Pegasus™ Computational Pattern Analytics (CPA) is an advanced high-performance, pattern-based technology suite comprising of mature production-proven flows and engines as well as new innovative approaches. Pegasus CPA includes feature rich capabilities in the pattern-search/classification/profiling domain while leveraging unique pattern engines such as Squish™ technology, machine-learning (ML), data analysis methods, Python-based scripting, and novel feature-extraction techniques. With Pegasus CPA, design and manufacturing teams can assess layout quality, automate design-quality improvements, accelerate design finishing prior to manufacturing, and develop powerful post-silicon layout analysis. Built-in features allow everyone from beginners to data scientists to leverage the power, capacity, and high performance of Pegasus CPA. Pegasus CPA delivers a richer feature set, more efficient processing capabilties,10-100X faster performance, and larger capacity than traditional DRC-based solutions.

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Benefits

High performance
  • Optimized algorithms and in-memory operations achieve unmatched processing speeds of up to 100X faster
  • Full-chip analysis capability for the largest layout databases in most advanced nodes in hours, not days
  • High-productivity CPA Studio GUI integrated in Pegasus Design Review enables faster analysis and dispositioning
Scalable
  • Scales linearly with area and number of CPUs
  • Easily handles from millions to billions of patterns, markers, and data sets
  • Cloud production proven
High capacity
  • Efficiently processes large full-chip layouts at the most advanced technology nodes
  • Full-chip processing, optimization, data mining, model training, and pattern harvesting
  • End-to-end flows have been developed to support up to billions of patterns with optimized CPU and memory usage
Production proven
  • In production use at major foundries to screen incoming tapeouts
  • Enables urgent and critical foundry production fixes
  • Foundation of pattern databases used to gather, monitor, and mitigate yield detractors
  • In-design optimizations using foundry kits improve the yield of incoming designs
Versatile applications
  • Streamlined design optimization
    • Single-pass, single-deck search and optimization
    • Find exact or similar patterns based on pattern banks or ML models
    • Automatically replace or optimize patterns during design implementation
    • Score patterns based on built-in or customer criteria
    • Increases recommended rules usage and DFM score using foundry kits to statistically improve yield
    • Integrated in Innovus™ Implementation System, Virtuoso® Layout Suite, and Pegasus Design Review Environment
    • Saves hours with automated DRC fixing
  • Interactive layout analysis
    • Interactive pattern capture, editing, search, profiling, and optimization integrated in Pegasus Design Review Environment
    • Allows quick deck development, update, and validation
    • Interactive GUI-driven flows with synchronized layout and results viewing
  • Pattern analytics, profiling, and classification
    • Automatically and quickly measures layout dimensions to generate pattern profiling reports and histograms
    • Efficient layout feature extraction is fed into ML engine for powerful layout analytics
    • Identifies most frequent patterns and outliers, and groups similar patterns
  • Yield detractor monitoring
    • ML-based hotspot prediction, feature extraction, and Python-based analytics
    • Creation and maintenance of pattern database of yield detractors, including pattern scoring, complexity analysis, and similarity
    • Enables systematic pattern-based dispositioning of yield detractors
  • Pattern capture, generation, and enumeration
    • Efficiently captures and compares full chip pattern databases with full coverage
    • Pattern comparison identifies new layout patterns in incoming product
    • Generates and varies patterns of interest within their context used for DRC deck validation and OPC calibration, and tests key generation for process hotspot coverage
  • Hierarchy injection
    • Creates hierarchical layout from flat layout or flattened layout
    • Recovers hierarchy from layout that has been flattened
    • Reduced database size and accelerates subsequent processing
Image showing Cadence Pattern Analysis Solution workbench
Cadence Pattern Analysis and Optimization Solution

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TRAINING COURSES

Process related yield risk mitigation with in-design pattern replacement for system ICs manufactured at Advanced technology nodes

 

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Application to DFM for Fabless: Design-Based Diffing, Pattern Analytics, and Risk Scoring
VIEW PRESENTATION
Pattern-Based Analytics to Estimate and Track Yield Risk of Designs Down to 7nm
VIEW PRESENTATION
Methodology for Analyzing and Quantifying Design Style Changes and Complexity Using Topological Patterns
VIEW PRESENTATION

GLOBALFOUNDRIES discusses how they collaborated with Cadence on pattern-matching technologies to accelerate full-chip DFM signoff.

  • Related Products

    • Pegasus CMP Predictor
    • Pegasus Critical Area Analyzer
    • Pegasus Layout Pattern Analyzer
    • Process Proximity Compensation
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News ReleasesVIEW ALL
  • Cadence Expands Collaboration with Arm to Accelerate Mobile Device Silicon Success 06/28/2022

  • Cadence Digital and Custom/Analog Design Flows Certified by TSMC for Latest N3E and N4P Processes 06/13/2022

  • Cadence Expands Collaboration with TSMC and Microsoft to Accelerate Timing Signoff for Giga-Scale Designs on the Cloud 12/01/2021

  • Cadence Integrity 3D-IC Platform Qualified by Samsung Foundry for Native 3D Partitioning Flow on 5LPE Design Stack 11/17/2021

  • Samsung Foundry Adopts New Tempus SPICE-Accurate Aging Analysis for High-Reliability Applications 11/16/2021

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