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  • 技術產品
    • DESIGN EXCELLENCE
      • 數位設計流程
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • 客製IC/類比/RF設計
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Virtuoso RF Solution
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus IC Power Integrity Solution
          • RESOURCES
          • Flows
      • 系統設計與驗證
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Emulation
          • Formal and Static Verification
          • FPGA-Based Prototyping
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
          • Palladium Z1 Enterprise Emulation Platform
          • Protium X1 Enterprise Prototyping Platform
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • Interface IP
          • Denali Memory IP
          • Tensilica Processor IP
          • Analog IP
          • System / Peripherals IP
          • Verification IP
      • IC封裝設計與分析
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • 系統分析
        • PRODUCT CATEGORIES
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Sigrity Advanced SI
          • Sigrity Advanced PI
          • RESOURCES
          • System Analysis Resources Hub
      • 嵌入式軟體
      • PCB設計與分析
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • What's New in Sigrity
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
    • PERVASIVE INTELLIGENCE
      • AI / 機器學習
      • AI IP系列
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Joules RTL Power Solution

Accurately measure RTL power consumption during design exploration

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Key Benefits

  • RTL within 15% of signoff power
  • Up to 20X faster time-based power analysis
  • Bridge between verification, implementation and signoff
  • Direct integration with Palladium platform for quick peak power identification
ASK US A QUESTION

 

Getting an accurate measure of RTL power consumption during design exploration has long been a major challenge for SoC design teams. System-level verification tools have the capacity to exercise real use cases, but they are disconnected from the implementation tools that translate RTL to gates and wires and from signoff tools that validate the final design.

Cadence® Joules™ RTL Power Solution closes this gap by delivering time-based RTL power analysis with system-level runtimes and capacity while still providing high-quality estimates of gates and wires.

Built on a multi-threaded frame-based architecture, the Joules RTL Power Solution delivers 20X faster time-based RTL power analysis as compared to other methods. The tool also incorporates rapid prototype technology from Cadence Genus™ Synthesis Solution that can analyze designs of up to 20 million instances overnight with gate-level accuracy of within 15 percent of signoff. In addition, the Joules RTL power solution integrates seamlessly with Cadence Palladium® Accelerator/Emulator for early system-level power analysis and optimization.

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TRAINING COURSES

Fast, Accurate RTL Power Analysis with Joules RTL Power Solution

  • Related Products

    • vManager Verification Management
    • Voltus IC Power Integrity Solution
    • Stratus High-Level Synthesis
    • Genus Synthesis Solution
    • Conformal Low Power
Videos

Building Cores with 10X Energy-Efficiency Improvement at REX Computing

Probing Power Problems Early at Fairchild Semiconductor

Joules Ideal Power – Using Power Scrubbers to Find and Fix Power Holes in RTL

Fast Accurate RTL Power Analysis with Joules RTL Power Solution

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