關鍵優勢

隨著設計複雜度及規模日益攀升，使得功耗、效能及面積(PPA)目標更具挑戰性。且隨著時程不斷壓縮，設計工作變得更加艱鉅。Cadence®數位全流程整合核心引擎和關鍵技術，領先業界跨越單點工具的限制，以整合的全流程協助客戶提前實現PPA目標。

Achieve Best PPA

Genus/Innovus iSpatial - Bridge synthesis and implementation with integrated core engines and unified physical optimization

Superior Signoff

Avoid bottlenecks and achieve the fastest path to predictable design closure

Design Creation

Start with an integrated flow that balances the architectural-level abstraction of the design alongside the detailed physical implementation constraints

Logic Equivalence Checking

Trusted, independent formal verification technology for fast, accurate bug detection and correction

Functional ECO

Delivering ECO automation for greater predictability and design convergence

Low-Power Validation

Delivering fast and accurate creation and verification of power intent

Synthesis

Creating the best balance of PPA

Power Analysis

Accurately measure RTL power consumption during design exploration

Constraints and CDC Signoff

A complete and efficient path to develop and manage constraints and clock-domain crossings (CDCs)

Test

Reducing SoC test time with a complete suite of industry-standard capabilities

Design Implementation

Achieve the best PPA with an implementation architecture that is integrated from design creation to signoff

Innovus Implementation and Floorplanning

Achieving rapid design convergence in large, complex chips requires greater capacity, accuracy, and automation

Superior Signoff

Achieve accuracy and faster design convergence with integrated engines and massively parallel, cloud-ready flow

Silicon Signoff and Verification

Electrical and physical verification tasks in an integrated, easy-to-use cloud-ready environment

Library Characterization

Ultra-fast cell library characterization solution for standard cells and complex I/Os

Technologies

3D-IC Design

Reduce power, raise performance, and get maximum functionality in a smaller form factor

Advanced Node

Innovative capabilities for digital designs at 20nm and below

Arm®-Based Designs

Digital design flows optimized for Arm-based applications

Low Power

Achieve power targets and signoff with confidence

Mixed-Signal Design

Comprehensive, interoperable, and proven mixed-signal verification and implementation

Resources

Video

應用iSpatial流程達到卓越設計: 工欲善其事，必先利其器

Article

Cracking Intractable Chip Design Challenges with the Help of Machine Learning

Article

Machine Learning in EDA Accelerates the Design Cycle

Video

Tempus™ Power Integrity “True Signoff”

Resources

white paper

Best Full-Flow PPA

Cadence revolutionized the way digital designers could solve their design challenges by revamping the entire digital tool suite with key enhancements to deliver faster turnaround time and best-in-class power, performance, and area (PPA) optimization.

Presentation

Quantus Extraction Solution for Accurate and Fast Silicon Signoff and Verification

Technical Brief

Quantus Smart View—Next-Generation Extracted View

News Release

Rockley Photonics Collaborates with Cadence to Create a High-Performance System for Hyperscale Data Centers

News ReleasesVIEW ALL

Rockley Photonics Collaborates with Cadence to Create a High-Performance System for Hyperscale Data Centers 12/02/2020

Cadence榮獲2020年四項台積電開放創新平台夥伴大獎 11/03/2020

Cadence Pegasus Verification System Certified for TSMC N16, N12 and N7 Process Technologies 10/08/2020

GLOBALFOUNDRIES Collaborates with Cadence on Availability of Mixed-Signal OpenAccess PDK for 22FDX Platform to Enable Advanced Mixed-Signal and mmWave Design 09/24/2020

Cadence Digital and Custom Flows Achieve Certification for TSMC N3 Process 08/25/2020