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CADENCE雲端方案

數位設計流程

Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

  • Logic Equivalence Checking
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客製IC/類比/RF設計

Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

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  • Solve analog simulation challenges in complex designs Watch Now
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系統設計與驗證

Cadence® system design and verification solutions, integrated under our Verification Suite, provide the simulation, acceleration, emulation, and management capabilities.

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  • Prototype your embedded software development Watch Now
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IP

An open IP platform for you to customize your app-driven SoC design.

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  • Solve the challenges of long-reach signaling with Cadence 112G SerDes IP Watch Now
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IC封裝設計與分析

Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.

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  • Four reasons to avoid multi-layer flip-chip pin padstacks Learn More

系統分析

Cadence® system analysis solutions provide highly accurate electromagnetic extraction and simulation analysis to ensure your system works under wide-ranging operating conditions.

  • See how to improve electrical-thermal co-simulation with the Celsius™ Thermal Solver Watch Now
  • Get true 3D system analysis with faster speeds, more capacity, and integration Watch Now
  • Electromagnetic Solutions
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嵌入式軟體

PCB設計與分析

Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

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  • Watch how to easily tackle complex and cutting edge designs. Learn More
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AI / 機器學習

AI IP系列

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See how our customers create innovative products with Cadence Explore Now

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TRAINING

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  • 技術產品
    • DESIGN EXCELLENCE
      • 數位設計流程
        • Logic Equivalence Checking
        • Innovus Implementation and Floorplanning
        • Functional ECO
        • Low-Power Validation
        • Synthesis
        • Power Analysis
        • Constraints and CDC Signoff
        • Silicon Signoff and Verification
        • Library Characterization
        • Test
        • Flows
      • 客製IC/類比/RF設計
        • Circuit Design
        • Circuit Simulation
        • Layout Design
        • Layout Verification
        • Library Characterization
        • RF / Microwave Solutions
        • Flows
      • 系統設計與驗證
        • Debug Analysis
        • Emulation
        • Formal and Static Verification
        • FPGA-Based Prototyping
        • Planning and Management
        • Simulation
        • Software-Driven Verification
        • Verification IP
        • System-Level Verification IP
        • Flows
      • IP
        • Interface IP
        • Denali Memory IP
        • Tensilica Processor IP
        • Analog IP
        • System / Peripherals IP
        • Verification IP
      • IC封裝設計與分析
        • Cross-Platform Co-Design and Analysis
        • IC Package Design
        • SI/PI Analysis
        • SI/PI Analysis Point Tools
        • Flows
    • SYSTEM INNOVATION
      • 系統分析
        • Electromagnetic Solutions
        • RF / Microwave Design
        • Thermal Solutions
        • System Analysis Resources Hub
      • 嵌入式軟體
      • PCB設計與分析
        • Design Authoring
        • PCB Layout
        • Library and Design Data Management
        • Analog/Mixed-Signal Simulation
        • SI/PI Analysis
        • SI/PI Analysis Point Tools
        • What's New in Allegro
        • What's New in Sigrity
        • RF / Microwave Design
        • Flows
        • Advanced PCB Design & Analysis Blog
        • Augmented Reality Lab Tools
    • PERVASIVE INTELLIGENCE
      • AI / 機器學習
      • AI IP系列
    • CADENCE雲端方案
  • 解決方案
      • INDUSTRIES
        • 5G 系統
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        • 先進製程
        • Arm-Based方案
        • Cloud Solutions
        • 低功耗方案
        • 混合訊號
        • Photonics
        • RF / Microwave
      • INDUSTRIES
        • 5G 系統
        • 航太與國防
        • 車用方案
        • AI / 機器學習
      • TECHNOLOGIES
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        • 先進製程
        • Arm-Based方案
        • Cloud Solutions
        • 低功耗方案
        • 混合訊號
        • Photonics
        • RF / Microwave
      • INDUSTRIES
        • 5G 系統
        • 航太與國防
        • 車用方案
        • AI / 機器學習
      • TECHNOLOGIES
        • 3D-IC 設計
        • 先進製程
        • Arm-Based方案
        • Cloud Solutions
        • 低功耗方案
        • 混合訊號
        • Photonics
        • RF / Microwave
      • INDUSTRIES
        • 5G 系統
        • 航太與國防
        • 車用方案
        • AI / 機器學習
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        • 3D-IC 設計
        • 先進製程
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        • RF / Microwave
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        • Custom IC / Analog / RF Design
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        • Tensilica Processor IP
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Spectre Accelerated Parallel Simulator

Delivering advanced SPICE-accurate simulation

Read Datasheet Read Case Study
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Key Benefits

  • Provides 10X-100X the single-thread performance (10X over Spectre Circuit Simulator) with out-of-box SPICE accuracy and convergence
  • Enables high-precision simulation for large, post-layout analog designs and subsystems without compromising accuracy
  • Delivers scalable performance with a multi-core architecture, allowing higher levels of analog design integration and verification
  • Uses foundry-certified device models (common across all simulation engines in the Virtuoso Multi-Mode Simulation solution) to ensure silicon-accurate analog designs
  • TÜV SÜD “Fit for Purpose – TCL1” certified to meet ISO 26262 automotive functional safety requirements

The Cadence® Spectre® Accelerated Parallel Simulator provides scalable performance and capacity—at full Spectre Circuit Simulator accuracy—for complex analog, RF, and mixed-signal blocks and subsystems with tens of thousands of devices.  

The Spectre Accelerated Parallel Simulator performs advanced SPICE-accurate simulation with faster convergence, scalable performance, and higher capacity. It is tightly integrated with the Cadence Virtuoso® custom IC design platform, allowing engineers to capture and pass design intent into the simulation environment, and it provides all the transistor-level analysis capabilities of the Spectre Circuit Simulator.

The proprietary full-matrix solving technology in the Spectre Accelerated Parallel Simulator delivers unparalleled scalability and multi-threading capability using modern multi-core compute platforms. These features and more ensure precise simulation without sacrificing accuracy of results.

Automotive TCL1 Certified for ISO 26262

The industry’s first analog/mixed-signal design implementation and verification flow to achieve “Fit for Purpose - Tool Confidence Level 1 (TCL1)” certification enables you to meet stringent ISO 26262 automotive safety requirements. The analog/mixed-signal design implementation and verification flow brings transistor-level designs from creation and simulation through physical implementation and verification using the Virtuoso ADE Product Suite and the Spectre Circuit Simulation Platform. For information on the safety manuals, Tool Confidence Analysis (TCA) documents, and compliance reports from TÜV SÜD, download the Functional Safety Documentation Kits through Cadence Online Support.

Contact Us

  • Related Products

    • Spectre Simulation Platform
    • Spectre eXtensive Partitioning Simulator (XPS)
    • Virtuoso ADE Product Suite
    • Spectre AMS Designer
    • Spectre RF Option
    • Virtuoso Schematic Editor
Resource Library

Press Releases (7)

  • Cadence Collaborates with TSMC to Advance 7nm FinFET Plus Design Innovation
  • Cadence Announces Legato Memory Solution, Industry’s First Integrated Memory Design and Verification Solution
  • Cadence Design Tools Certified for TSMC 7nm Design Starts and 10nm Production
  • Cadence and Intel Collaborate to Release 14nm Library Characterization Reference Flow for Customers of Intel Custom Foundry
  • TSMC Adopts Cadence Solutions for 16nm FinFET Library Characterization
  • ARM Implements the Cadence Library Characterization Solution for Advanced Node Foundation IP Development
  • Cadence Characterization Solution for Complex Multi-bit Cells Delivers Power and Performance Benefits for Yamaha

Video (1)

  • Combined MathWorks and Cadence Design Flow for Analog/Mixed-Signal IC Development

Customers Success (2)

  • Cadence and Texas Instruments Success Story
  • Cadence and Rohde & Schwarz Success Story

Webinar (1)

  • Combined MathWorks and Cadence Design Flow for Analog/Mixed-Signal IC Development
VIEW ALL
News ReleasesVIEW ALL
  • Cadence Collaborates with TSMC to Advance 7nm FinFET Plus Design Innovation 09/11/2017

  • Cadence Announces Legato Memory Solution, Industry’s First Integrated Memory Design and Verification Solution 09/06/2017

  • Cadence Design Tools Certified for TSMC 7nm Design Starts and 10nm Production 03/14/2016

  • Cadence and Intel Collaborate to Release 14nm Library Characterization Reference Flow for Customers of Intel Custom Foundry 03/16/2015

  • TSMC Adopts Cadence Solutions for 16nm FinFET Library Characterization 09/02/2014

Blogs VIEW ALL
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