- Comprehensive library characterization system including variation modeling and library validation for standard cells and complex I/Os
- Ability to characterize multi-PVT corners in the same run
- Generate statistical libraries in LVF along with nominal using the unified flow
- Machine learning prediction delivers shorter characterization turnaround time (TAT)
- Cloud enablement with massive distribution and parallelization algorithms for faster throughput
- Advanced aging characterization to enable Tempus™ Aging-Aware STA
The Cadence® Liberate™ Trio™ Characterization Suite is the industry’s first unified library characterization system that brings together characterization, variation modeling, and library validation for standard cells, custom cells, multi-bits, and I/Os. The Liberate Trio Suite includes multi-PVT and unified flows that achieve both accuracy and high-speed performance. Its powerful combination of patented technology for generating and optimizing characterization stimulus and parallel processing capability takes advantage of enterprise-wide compute resources, and it leverages cloud resources for an enormous collection of libraries. The Liberate Trio suite is your one-stop-shop for all aspects of standard cell library characterization and validation.
Unified Library Characterization System
The Liberate Trio suite combines our tested and proven characterization suite with some of the most advanced technology available today in a unified library characterization system.
The Liberate Trio suite provides a multi-PVT flow to characterize multiple corners in the same run with the resulting libraries maintaining consistency in structure. Vectors and modeling attributes extracted from standard cell circuit analysis are shared among all corners to reduce runtime and ensure the structural symmetry need for static timing analysis (STA) scaling applications. This simplifies the challenge of dealing with an enormous collection of corners across libraries.
Statistical libraries in Liberty Variation Format (LVF) and nominal libraries can now be generated using a unified characterization run that shares statistical and nominal SPICE process models. This flow eliminates the need to merge libraries at the end of a statistical run and the combined characterization run improves performance.
The sooner designers have the complete set of corners characterized, the earlier they can start design implementation and close timing. The machine learning algorithms in the Liberate Trio suite enable prediction of critical corners through clustering techniques to determine which corners need to be characterized. The use of machine learning significantly reduces the number of libraries that will need to be fully characterized while ensuring accuracy using ML prediction. With the Liberate ML option’s “prediction out”, intermediate PVTs can be quickly and accurately derived from fully characterized libraries, providing a more comprehensive set of corners to design teams. The Liberate ML option’s “prediction in” also speeds up the entire characterization TAT and reduces the number of CPUs required to deliver a complete accurate characterized library set. The Liberate ML option is shifting left the entire design cycle.
Characterization of large libraries that would normally take weeks can now be turned around in days. Thoroughly distributed and massively parallel, our library characterization portfolio has been fully optimized to run on cloud-based servers by making characterization processes. The Liberate Trio suite can be used on leading cloud service providers or a company’s private cloud and is scalable to over thousands of CPUs.
The Cadence advanced aging solution consists of the characterization of stress condition-independent cell libraries that are used by the Tempus aging-aware STA and deliver aging-aware timing and optimization for digital designs. Unlike global derating or corner-based aging characterization, this advanced aging solution, designed from the ground up, relies on the Liberate Trio suite to characterize a generic, stress condition-independent cell library. The Liberate Trio suite’s advanced aging model enables Tempus aging-aware STA to support dependency of timing degradation on aging context, non-inform aging where stress condition is different than operating condition, and arbitrary target usage profiles (segments of supply voltage, temperature, and age) without computing-intensive re-characterization.
- Utilizes a single script to characterize all PVT corners in a library using multi-PVT flow
- Statistical and nominal libraries unified in a single characterization run
- Efficient multiprocessing delivers 3X runtime improvements for library sets
- Machine learning option predicts critical corners and intermediate PVTs and accelerates the overall characterization runtime and hardware requirements
- Advanced-aging characterization of stress condition-independent cell libraries for Tempus aging-aware STA
- Runtime metrics and results monitoring with a sleek new GUI cockpit
Press Releases (13)
- Samsung Foundry Adopts Cadence Liberate Trio Characterization Suite for 3nm Production Library
- Samsung Foundry Adopts New Tempus SPICE-Accurate Aging Analysis for High-Reliability Applications
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- Cadence Collaborates with TSMC to Accelerate 5nm FinFET Innovation, Enabling Next-Generation SoC Production Design
- Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies to Facilitate Mobile and HPC Design Creation
- Cadence Launches Liberate Trio Characterization Suite Employing Machine Learning and Cloud Optimizations
- Cadence Collaborates with TSMC to Advance 5nm and 7nm+ Mobile and HPC Design Innovation
- Cadence Achieves TÜV SÜD’s First Comprehensive “Fit for Purpose - TCL1” Certification in Support of Automotive ISO 26262 Standard
- Cadence Tools and Flows Achieve Production-Ready Certification for TSMC’s 12FFC Process
- Cadence Custom/Analog and Full-Flow Digital and Signoff Tools Enabled for GLOBALFOUNDRIES 7LP Process Node
- Cadence and TSMC Advance 7nm FinFET Designs for Mobile and HPC Platforms
- Cadence Design Tools Certified for TSMC 7nm Design Starts and 10nm Production