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Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

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  • 技術產品
    • DESIGN EXCELLENCE
      • 數位設計流程
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
          • Voltus IC Power Integrity Solution
      • 客製IC/類比/RF設計
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • 系統設計與驗證
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
      • IP
        • PRODUCT CATEGORIES
          • Denali Memory Interface and Storage IP
          • 112G/56G SerDes
          • PCIe and CXL
          • Tensilica Processor IP
          • Chiplet and D2D
          • Interface IP
        • RESOURCES
          • Discover PCIe
      • IC封裝設計與分析
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
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        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
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          • RF / Microwave Design
          • Signal and Power Integrity
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          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
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          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • 嵌入式軟體
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        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
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          • Advanced PCB Design & Analysis Resources Hub
          • Flows
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Liberate Characterization Solution

High-performance characterization engine for standard cells, memories, and AMS blocks

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Key Benefits

  • Unparalleled operational efficiency and user flexibility with highly scalable systems
  • Advanced compiler, predictable runtime, and debug capabilities
  • TÜV SÜD “Fit for Purpose – TCL1” certified to meet ISO 26262 automotive functional safety requirements
ASK US A QUESTION

 

Cadence® Liberate™ characterization solution is an ultra-fast standard cell, I/O, and complex multi-bit-cell library characterization solution. As part of Cadence’s complete custom solution for library characterization, it generates electrical cell views for timing, power, and signal integrity, including advanced current source models (CCS and ECSM). 

  • Conference paper: Intelligent Characterization Methodology for MBFF Runtime Reduction (log-in required)
  • Conference paper: Accelerating Library Characterization Through Infrastructure Optimization (log-in required)

Automotive TCL1 Certified for ISO 26262

The industry’s first digital implementation and signoff flow to achieve “Fit for Purpose - Tool Confidence Level 1 (TCL1)” certification enables you to meet stringent ISO 26262 automotive safety requirements. The Liberate Characterization Solution is part of the flow covering RTL-to-GDSII implementation and signoff. For information on the safety manuals, Tool Confidence Analysis (TCA) documents, and compliance reports from TÜV SÜD, download the Functional Safety Documentation Kits through Cadence Online Support.

Features

  • Patented InsideView approach automatically pre-characterizes each cell using transistor-level circuit analysis to learn all internal logic states
  • Enables automatic vector generation (AVG)
  • Ensures a complete, accurate, and highly efficient characterization of library cells
  • Supports complex cells including those required for high-speed and/or low-power design, such as pulse latches, multi-bit flip-flop arrays, level shifters, power switches, and cells with sleep modes

Contact Us

GlobalFoundries’ Siddharth Sawant shares insights on the aging mechanisms and best approach to achieve highly accurate aging data models using the Cadence Liberate Characterization Solution.

  • Related Products

    • Liberate MX Memory Characterization
    • Liberate LV Library Validation Solution
    • Liberate AMS Mixed-Signal Characterization
    • Spectre Accelerated Parallel Simulator
    • Liberate Variety Statistical Characterization
    • Spectre eXtensive Partitioning Simulator (XPS)
    • Spectre Circuit Simulator
  • Related Information

    • Addressing Memory Characterization Capacity and Throughput Requirements with Dynamic Partitioning White Paper
Resource Library

Press Releases (17)

  • Cadence Digital and Custom/Analog Flows Achieve the Latest TSMC N3 and N4 Certifications | Cadence
  • Cadence Digital and Custom Flows Achieve Certification for TSMC N3 Process | Cadence
  • Cadence Achieves Digital and Custom/Analog EDA Flow Certification for TSMC N6 and N5 Process Technologies | Cadence
  • Cadence Automotive Reference Flow Certified by Samsung Foundry for Advanced-Node Design Creation | Cadence
  • Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies to Facilitate Mobile and HPC Design Creation | Cadence
  • Cadence Launches Liberate Trio Characterization Suite Employing Machine Learning and Cloud Optimizations | Cadence
  • Cadence Collaborates with TSMC to Advance 5nm and 7nm+ Mobile and HPC Design Innovation | Cadence
  • Cadence Achieves TÜV SÜD’s First Comprehensive “Fit for Purpose - TCL1” Certification in Support of Automotive ISO 26262 Standard | Cadence
  • Cadence Tools and Flows Achieve Production-Ready Certification for TSMC’s 12FFC Process | Cadence
  • Cadence Announces Legato Memory Solution, Industry’s First Integrated Memory Design and Verification Solution | Cadence
  • Cadence Custom/Analog and Full-Flow Digital and Signoff Tools Enabled for GLOBALFOUNDRIES 7LP Process Node | Cadence
  • Cadence and TSMC Advance 7nm FinFET Designs for Mobile and HPC Platforms | Cadence
  • Cadence Design Tools Certified for TSMC 7nm Design Starts and 10nm Production | Cadence
  • Cadence and Intel Collaborate to Release 14nm Library Characterization Reference Flow for Customers of Intel Custom Foundry | Cadence
  • TSMC Adopts Cadence Solutions for 16nm FinFET Library Characterization | Cadence
  • ARM Implements the Cadence Library Characterization Solution for Advanced Node Foundation IP Development | Cadence
  • Cadence Characterization Solution for Complex Multi-bit Cells Delivers Power and Performance Benefits for Yamaha | Cadence

White Paper (1)

  • Addressing Memory Characterization Capacity and Throughput Requirements with Dynamic Partitioning White Paper

Datasheet (1)

  • Liberate Characterization Portfolio Datasheet

Presentation (1)

  • Quantus Extraction Solution for Accurate and Fast Silicon Signoff and Verification

Customers Success (1)

  • Cadence and Texas Instruments Success Story
VIEW ALL
Videos

GlobalFoundries Expert Insights: Aging Analysis for IoT and Automotive Applications

Invecas Provides Electromigration-Based Maximum Capacitance Limits for Standard Cell Library Using Cadence Virtuoso Liberate Characterization Solution

Ultra-Low Voltage SRAM: Addressing the Characterization Challenge

Getting What You’re Entitled to at 10nm by Reducing Timing Pessimism

Characterizing 22FDX Library at GLOBALFOUNDRIES

Faster Timing Characterization of Analog Macros

Liberate MX Product Demonstration

Accurate and Faster SoC Signoff with Simulation-Based AMS Characterization

Statistical Characterization Approach Using Liberate MX with 40nm Low Voltage SRAM

News ReleasesVIEW ALL
  • Cadence Digital and Custom/Analog Flows Achieve the Latest TSMC N3 and N4 Certifications 10/21/2021

  • Cadence Digital and Custom Flows Achieve Certification for TSMC N3 Process 08/25/2020

  • Cadence Achieves Digital and Custom/Analog EDA Flow Certification for TSMC N6 and N5 Process Technologies 06/02/2020

  • Cadence Automotive Reference Flow Certified by Samsung Foundry for Advanced-Node Design Creation 10/17/2019

  • Cadence Collaborates with TSMC to Advance 5nm and 7nm+ Mobile and HPC Design Innovation 05/01/2018

Blogs VIEW ALL
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