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數位設計流程

Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

PRODUCT CATEGORIES

  • Logic Equivalence Checking
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客製IC/類比/RF設計

Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

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FEATURED PRODUCTS

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系統設計與驗證

Offering a full verification flow to our customers and partners that delivers the highest verification throughput in the industry

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IP

An open IP platform for you to customize your app-driven SoC design.

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IC封裝設計與分析

Driving efficiency and accuracy in advanced packaging, system planning, and multi-fabric interoperability, Cadence® package implementation products deliver the automation and accuracy.

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系統分析

Cadence® system analysis solutions provide highly accurate electromagnetic extraction and simulation analysis to ensure your system works under wide-ranging operating conditions.

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嵌入式軟體

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Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

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ZH - Taiwan
  • US - English
  • China - 简体中文
  • Japan - 日本語
  • Korea - 한국어
  • 技術產品
    • DESIGN EXCELLENCE
      • 數位設計流程
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • 客製IC/類比/RF設計
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Virtuoso RF Solution
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus IC Power Integrity Solution
          • RESOURCES
          • Flows
      • 系統設計與驗證
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Emulation and Prototyping
          • Formal and Static Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • Interface IP
          • Denali Memory IP
          • Tensilica Processor IP
          • Analog IP
          • System / Peripherals IP
          • Verification IP
      • IC封裝設計與分析
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • 系統分析
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Omnis
          • Sigrity Advanced SI
          • Sigrity Advanced PI
          • RESOURCES
          • System Analysis Resources Hub
          • AWR Software Download Free Trial
      • 嵌入式軟體
      • PCB設計與分析
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • What's New in Sigrity
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
    • PERVASIVE INTELLIGENCE
      • AI / 機器學習
      • AI IP系列
    • CADENCE雲端方案
    • VIEW ALL PRODUCTS
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        • 5G 系統
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        • 先進製程
        • Arm-Based方案
        • Cloud Solutions
        • 低功耗方案
        • 混合訊號
        • Photonics
        • RF / Microwave
      • Industries
        • 5G 系統
        • 航太與國防
        • 車用方案
        • AI / 機器學習
      • Technologies
        • 3D-IC 設計
        • 先進製程
        • Arm-Based方案
        • Cloud Solutions
        • 低功耗方案
        • 混合訊號
        • Photonics
        • RF / Microwave
      • Industries
        • 5G 系統
        • 航太與國防
        • 車用方案
        • AI / 機器學習
      • Technologies
        • 3D-IC 設計
        • 先進製程
        • Arm-Based方案
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        • 低功耗方案
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      • Support
        • Support Process
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      • Support
        • Support Process
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Library Characterization

Ultra-fast cell library characterization solution for standard cells and complex I/Os

  • Library Characterization

    • Liberate Trio Characterization Suite
    • Liberate MX Memory Characterization
    • Liberate AMS Mixed-Signal Characterization
    • Spectre Accelerated Parallel Simulator

Designing at nanometer process technologies—and especially at advanced nodes (28nm and below)—requires many additional library views in order to achieve high-quality silicon and avoid silicon re-spins due to inaccurate signoff analysis. For accurate modeling of instance-specific voltage variation or temperature gradients, it’s vital to characterize each library at multiple voltages and multiple temperatures, increasing the total number of library corners. For the most advanced processes, it is becoming common to offer alternative cell libraries that improve yield at the expense of area and performance. As a result, creating and maintaining all of these library views is becoming a major bottleneck in the design flow.

Cadence provides a library characterization flow centered on the Cadence® Characterization portfolio. Adopted by major customers around the world, the suite includes the Liberate™  Trio Characterization Suite, Liberate MX Memory Characterization, and Liberate AMS Mixed-Signal Characterization as well as stand-alone options for Liberate LV Library Validation Solution, Liberate Variety™ Statistical Characterization, and Liberate Characterization. The portfolio delivers the industry’s most complete and robust solutions for the characterization, variation modeling, and validation of your foundation IP, from standard cells, I/Os, and complex multi-bit cells to memories and mixed-signal blocks. Cadence’s patented InsideView technology delivers better correlation to silicon by improving library throughput and ensuring timing, power, noise, and statistical coverage of your IP. The Characterization portfolio also integrates with the Cadence Spectre® Circuit Simulator, the industry-standard SPICE simulator, delivering even greater throughput with the accuracy required for advanced-node libraries.

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