Designing at nanometer process technologies—and especially at advanced nodes (28nm and below)—requires many additional library views in order to achieve high-quality silicon and avoid silicon re-spins due to inaccurate signoff analysis. For accurate modeling of instance-specific voltage variation or temperature gradients, it’s vital to characterize each library at multiple voltages and multiple temperatures, increasing the total number of library corners. For the most advanced processes, it is becoming common to offer alternative cell libraries that improve yield at the expense of area and performance. As a result, creating and maintaining all of these library views is becoming a major bottleneck in the design flow.
Cadence provides a library characterization flow centered on the Cadence® Characterization portfolio. Adopted by major customers around the world, the suite includes the Liberate™ Trio Characterization Suite, Liberate MX Memory Characterization, and Liberate AMS Mixed-Signal Characterization as well as stand-alone options for Liberate LV Library Validation Solution, Liberate Variety™ Statistical Characterization, and Liberate Characterization. The portfolio delivers the industry’s most complete and robust solutions for the characterization, variation modeling, and validation of your foundation IP, from standard cells, I/Os, and complex multi-bit cells to memories and mixed-signal blocks. Cadence’s patented InsideView technology delivers better correlation to silicon by improving library throughput and ensuring timing, power, noise, and statistical coverage of your IP. The Characterization portfolio also integrates with the Cadence Spectre® Circuit Simulator, the industry-standard SPICE simulator, delivering even greater throughput with the accuracy required for advanced-node libraries.