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Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

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  • 技術產品
    • DESIGN EXCELLENCE
      • 數位設計流程
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
          • Voltus IC Power Integrity Solution
      • 客製IC/類比/RF設計
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • 系統設計與驗證
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
      • IP
        • PRODUCT CATEGORIES
          • Denali Memory Interface and Storage IP
          • 112G/56G SerDes
          • PCIe and CXL
          • Tensilica Processor IP
          • Chiplet and D2D
          • Interface IP
        • RESOURCES
          • Discover PCIe
      • IC封裝設計與分析
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • 系統分析
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • 嵌入式軟體
      • PCB設計與分析
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
      • Computational Fluid Dynamics
    • PERVASIVE INTELLIGENCE
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      • Industries
        • 5G 系統
        • 航太與國防
        • 車用方案
        • Hyperscale Computing
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        • 3D-IC 設計
        • 先進製程
        • AI / 機器學習
        • Arm-Based方案
        • Cloud Solutions
        • Computational Fluid Dynamics
        • Functional Safety
        • 低功耗方案
        • 混合訊號
        • Photonics
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      • Industries
        • 5G 系統
        • 航太與國防
        • 車用方案
        • Hyperscale Computing
      • Technologies
        • 3D-IC 設計
        • 先進製程
        • AI / 機器學習
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Virtuoso DFM Interactive

Fast silicon convergence

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Key Benefits

  • Foundry-golden, comprehensive, model-based litho hotspot analysis
  • Industry’s first in-design, constraint-driven layout-dependent-effects variability detection and optimization
  • Higher productivity and more predictable tapeout schedules

Cadence® Virtuoso® DFM enables designers to accurately assess both physical and electrical variability to ensure the manufacturability of custom and mixed-signal designs, libraries, and IP—without ever leaving the Virtuoso Layout Suite environment.

Virtuoso DFM preserves design intent (such as electrical constraints), ensures fast convergence on design goals through accurate abstraction, and provides highly convergent results through near-linear scalability and automatic fixing of errors. This enables engineers to implement a “correct-by-design” flow, so they can efficiently and predictably reach tapeout on leading-edge designs with multiple foundry partners.

Virtuoso DFM allows designers to identify, analyze, and automatically optimize the design’s on-chip parameters for the impact of physical effects such as lithography, mask, OPC, etch, and RET; as well as layout-dependent effects such as litho, overlay, context-dependent stress, strain, well proximity, unintentional stressors like shallow-trench isolation, contact-to-contact spacing, and more. In addition, the Virtuoso in-design methodology provides an accurate, model-based flow for designers to minimize the impact of manufacturing variations on design performance.

Features

  • Minimizes design iterations with slack-driven engine
  • Handles large designs through massively parallel architecture
  • Improves cross-corner variability
  • In-design DFM and predictable DFM closure for custom design implementation
  • Production-proven “golden” pattern matcher for in-design DRC+ for GLOBALFOUNDRIES 28nm process

Contact Us

  • Related Products

    • Physical Verification System
    • Quantus Extraction Solution
    • Virtuoso Integrated Physical Verification System
    • LDE Electrical Analyzer
    • Pegasus Layout Pattern Analyzer
News ReleasesVIEW ALL
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  • Cadence Expands Collaboration with Arm to Accelerate Mobile Device Silicon Success 06/28/2022

  • Cadence and Intel Foundry Services Collaborate to Accelerate Innovation with Scalable and Proven Cadence Cloud Solutions 06/28/2022

  • Cadence Achieves PCIe 5.0 Specification Compliance for PHY and Controller IP in TSMC Advanced Technologies 06/21/2022

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