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  • 技術產品
    • DESIGN EXCELLENCE
      • 數位設計流程
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • 客製IC/類比/RF設計
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          • Circuit Design
          • Circuit Simulation
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          • RF / Microwave Solutions
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          • Spectre X Simulator
          • Virtuoso RF Solution
          • Virtuoso Layout Suite
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          • Voltus IC Power Integrity Solution
          • RESOURCES
          • Flows
      • 系統設計與驗證
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Emulation
          • Formal and Static Verification
          • FPGA-Based Prototyping
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
          • Palladium Z1 Enterprise Emulation Platform
          • Protium X1 Enterprise Prototyping Platform
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • Interface IP
          • Denali Memory IP
          • Tensilica Processor IP
          • Analog IP
          • System / Peripherals IP
          • Verification IP
      • IC封裝設計與分析
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
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          • Electromagnetic Solutions
          • RF / Microwave Design
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Sigrity Advanced SI
          • Sigrity Advanced PI
          • RESOURCES
          • System Analysis Resources Hub
      • 嵌入式軟體
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          • Design Authoring
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          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • What's New in Sigrity
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
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Virtuoso Layout Suite

Accelerated full custom IC layout

Read GXL Datasheet Read XL Datasheet
  • Overview
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Key Benefits

  • Supports custom analog, digital, and mixed-signal designs at the device, cell, block, and chip levels
  • Accelerated performance and productivity from advanced full custom polygon editing through more flexible schematic and constraint-driven assisted full custom layout, to full custom layout automation
  • Enables creation of differentiated custom silicon that is both fast and silicon accurate

As the full custom IC layout suite of the industry-leading Cadence® Virtuoso® platform, the Virtuoso Layout Suite supports custom analog, digital, and mixed-signal designs at the device, cell, block, and chip levels. The enhanced Virtuoso Layout Suite offers accelerated performance and productivity from advanced full custom polygon editing (L) through more flexible schematic-driven and constraint-driven assisted full custom layout (XL), to full custom layout automation (GXL). Seamlessly integrated with the Virtuoso Schematic Editor and the Virtuoso Analog Design Environment, the Virtuoso Layout Suite enables the creation of differentiated custom silicon that is both fast and silicon accurate.

The Virtuoso platform is the industry’s most silicon-proven, comprehensive, custom IC design platform, trusted in taping out thousands of designs each year for more than 25 years.

  • Virtuoso Layout Suite L Datasheet
  • Virtuoso Layout Suite XL Datasheet
  • Virtuoso Layout Suite GXL Datasheet

Features

  • New patented Virtuoso Layout Suite L graphics-rendering engine provides from 10X to 100X accelerated zoom, fit, pan, drag, and redraw performance on large layouts
  • New Virtuoso Layout Suite XL connectivity extractor technology accelerates trace net, probe net, and mark net performance from 10X to 50X on large layouts
  • Patented multi-user Express PCell capability continues to boost design opening performance from 10X to 20X whenever users require PCell evaluation
  • New patented stream-in engine provides accelerated performance from 2X to 20X
  • Virtuoso Layout Suite GXL Space-Based Routing technology automatically enforces process and design rules during interactive and assisted wire and bus editing
  • Virtuoso Layout Suite GXL ModGens (module generators) add a new interactive pattern-manipulation flow, making real-time customization of a high-precision structured layout very visual and simple
  • Virtuoso Layout Suite GXL Space-Based Routing technology at chip levels can deliver high-quality constraint-driven specialty routing to close thousands of nets in minutes, and new structured device-level routing capabilities that can enhance routing productivity by as much as 50%
  • The Virtuoso platform is backed by the largest number of process design kits (PDKs) available from the world’s leading foundries, for process nodes everywhere from mature 0.6µm to advanced 7nm process nodes
Vituoso Layout Suite XL

Contact Us

  • Related Products

    • Virtuoso Schematic Editor
    • Virtuoso ADE Product Suite
    • Custom/Analog Advanced Node
    • Virtuoso Layout Suite EAD
    • Virtuoso Space-Based Router
    • Silicon Signoff and Verification
    • Virtuoso Digital Implementation
Resource Library

Press Releases (21)

  • GLOBALFOUNDRIES Collaborates with Cadence on Availability of Mixed-Signal OpenAccess PDK for 22FDX Platform to Enable Advanced Mixed-Signal and mmWave Design
  • Cadence Digital and Custom Flows Achieve Certification for TSMC N3 Process
  • Cadence to Acquire AWR Corporation from National Instruments to Accelerate System Innovation for 5G RF Communications
  • Cadence and National Instruments Enter into Strategic Alliance Agreement to Enhance Electronic System Innovation
  • Cadence Custom/AMS Flow Certified for Samsung 5LPE Process Technology
  • Cadence Design Solutions Certified for TSMC-SoIC Advanced 3D Chip Stacking Technology
  • Cadence Collaborates with TSMC to Accelerate 5nm FinFET Innovation, Enabling Next-Generation SoC Production Design
  • Cadence Custom/AMS Flow Certified on Samsung 7LPP Process Technology
  • Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies to Facilitate Mobile and HPC Design Creation
  • Cadence Supports New TSMC WoW Advanced Packaging Technology
  • Cadence Full-Flow Digital and Signoff Tools and Custom/Analog Tools Certified and Enabled for Intel 22FFL Process Technology
  • Cadence Tools and Flows Achieve Production-Ready Certification for TSMC’s 12FFC Process
  • Cadence Collaborates with TSMC to Advance 7nm FinFET Plus Design Innovation
  • Cadence Custom/Analog and Full-Flow Digital and Signoff Tools Enabled for GLOBALFOUNDRIES 7LP Process Node
  • Cadence Custom/Analog, Digital and Signoff Tools Achieve Certification on Samsung 28FDS Process Technology
  • Cadence Digital, Signoff and Custom/Analog Tools Enabled on Samsung’s 7LPP and 8LPP Process Technologies
  • Cadence Unveils Next-Generation Virtuoso Platform Featuring Advanced Analog Verification Technologies and 10X Performance Improvements Across Platform
  • Silicon Labs Significantly Reduces Design Time Using the Cadence Mixed-Signal Low-Power Flow
  • Cadence Collaborates with Lumerical and PhoeniX Software to Offer Virtuoso Platform-Based Design Flow for Electronic /Photonic ICs
  • Cadence Unveils Virtuoso Advanced-Node Platform for 10nm Processes
  • Cadence and Intel Collaborate to Release 14nm Library Characterization Reference Flow for Customers of Intel Custom Foundry

Presentation (2)

  • Advanced Custom Layout Methodologies
  • New Virtuoso Design Platform

Datasheet (4)

  • Virtuoso Layout Suite GXL Datasheet
  • Virtuoso Layout Suite L Datasheet
  • Virtuoso Layout Suite for Electrically Aware Design Datasheet
VIEW ALL
Videos

Toshiba Electronic Device Solutions Overcomes Complexities of Advanced-Node Designs

Analog Devices Automates and Accelerates Layout with Virtuoso Platform

STMicroelectronics - Improving Productivity with Virtuoso SPD

Validating Design Intent and Improving Design Quality at Micron

Celebrating 25 Years of Virtuoso Innovation

Fairchild Semiconductor Eases Floorplanning Challenges of Mixed-Signal Design with Virtuoso Platform

Using VSR for Chip Routing on ST smARTpower Technologies

Cadence In-Design DFM-LDE Adoption in ST SmartPower PDK

Place-and-Route in Under a Day for Allegro Microsystems

News ReleasesVIEW ALL
  • GLOBALFOUNDRIES Collaborates with Cadence on Availability of Mixed-Signal OpenAccess PDK for 22FDX Platform to Enable Advanced Mixed-Signal and mmWave Design 09/24/2020

  • Cadence Digital and Custom Flows Achieve Certification for TSMC N3 Process 08/25/2020

  • Cadence to Acquire AWR Corporation from National Instruments to Accelerate System Innovation for 5G RF Communications 12/02/2019

  • Cadence and National Instruments Enter into Strategic Alliance Agreement to Enhance Electronic System Innovation 12/02/2019

  • Cadence Custom/AMS Flow Certified for Samsung 5LPE Process Technology 10/17/2019

Blogs VIEW ALL
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