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  • 技術產品
    • DESIGN EXCELLENCE
      • 數位設計流程
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
          • Voltus IC Power Integrity Solution
      • 客製IC/類比/RF設計
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • 系統設計與驗證
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
      • IP
        • PRODUCT CATEGORIES
          • Denali Memory Interface and Storage IP
          • 112G/56G SerDes
          • PCIe and CXL
          • Tensilica Processor IP
          • Chiplet and D2D
          • Interface IP
        • RESOURCES
          • Discover PCIe
      • IC封裝設計與分析
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
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          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
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          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • 嵌入式軟體
      • PCB設計與分析
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
      • Computational Fluid Dynamics
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Virtuoso Layout Suite EAD

Avoid multiple design iterations with real-time feedback

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Key Benefits

  • Performs real-time analysis and optimization with built-in interconnect parasitic extraction engine that instantly evaluates your layout as it is created
  • Enables you to set electrical constraints and observe, in real time, whether these constraints are being met
  • Alerts you to electromigration issues that are created as your layout is drawn
  • Minimizes respins and “over design” via partial layout resimulation of existing interconnect parasitics
  • Reduces circuit design cycle by up to 30 percent
  • Enables you to optimize chip performance and utilize less area

Featuring a unique in-design electrical verification capability, the Cadence® Virtuoso® Layout Suite for Electrically Aware Design (EAD) enhances design team productivity and circuit performance for custom ICs.

With Virtuoso Layout Suite EAD, you’ll have the technology and methodology to avoid multiple design iterations and “over design.” You’ll be able to monitor electrical issues while your layout is created, and to electrically analyze, simulate, and verify interconnect decisions in real time. As a result, you’ll be able to achieve electrically correct-by-construction layout. The solution’s unique in-design electrical verification capability lets you reduce your circuit design cycle by up to 30 percent and achieve better chip performance in less area.

With Virtuoso Layout Suite EAD, you can save days to weeks of design time. The solution extracts interconnect parasitics in real time and works with partial designs. Layout and circuit designers will be able to collaborate more efficiently with enhanced real-time visibility into electrical issues. Because the solution works seamlessly with other tools in the Virtuoso platform, you’ll be able to capture currents and voltages from simulations run in Virtuoso Analog Design Environment, and pass this electrical information into the layout environment.

Refer to Blog post: Virtuoso Electrically Aware Design (EAD)—A New Approach to Custom/Analog Layout

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Virtuoso Layout Suite EAD Editing

Contact Us

Learn how to improve designs with a custom layout providing in-design, real-time interconnect parasitic extraction and analysis

  • Related Products

    • Virtuoso Layout Suite
    • Virtuoso Schematic Editor
    • Virtuoso ADE Product Suite
    • Virtuoso ADE Assembler
    • Virtuoso ADE Verifier
    • Virtuoso Variation Option
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News ReleasesVIEW ALL
  • Cadence Integrity 3D-IC Platform Supports TSMC 3DFabric™ Technologies for Advanced Multi-Chiplet Designs 10/26/2021

  • Cadence Custom/AMS Flow Certified for Samsung 5LPE Process Technology 10/17/2019

  • Cadence Design Solutions Certified for TSMC-SoIC Advanced 3D Chip Stacking Technology 04/23/2019

  • Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies to Facilitate Mobile and HPC Design Creation 10/01/2018

  • Cadence Expands Virtuoso Platform with Enhanced System Design, Advanced Node Support down to 5nm, and Simulation-Driven Layout 04/10/2018

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