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數位設計流程

Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

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Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

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系統設計與驗證

Offering a full verification flow to our customers and partners that delivers the highest verification throughput in the industry

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An open IP platform for you to customize your app-driven SoC design.

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Cadence® system analysis solutions provide highly accurate electromagnetic extraction and simulation analysis to ensure your system works under wide-ranging operating conditions.

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Cadence® PCB design solutions enable shorter, more predictable design cycles with greater integration of component design and system-level simulation for a constraint-driven flow.

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ZH - Taiwan
  • US - English
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  • 技術產品
    • DESIGN EXCELLENCE
      • 數位設計流程
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • 客製IC/類比/RF設計
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Virtuoso RF Solution
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus IC Power Integrity Solution
          • RESOURCES
          • Flows
      • 系統設計與驗證
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Emulation and Prototyping
          • Formal and Static Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • Interface IP
          • Denali Memory IP
          • Tensilica Processor IP
          • Analog IP
          • System / Peripherals IP
          • Verification IP
      • IC封裝設計與分析
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • 系統分析
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Omnis
          • Sigrity Advanced SI
          • Sigrity Advanced PI
          • RESOURCES
          • System Analysis Resources Hub
          • AWR Software Download Free Trial
      • 嵌入式軟體
      • PCB設計與分析
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • What's New in Sigrity
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
    • PERVASIVE INTELLIGENCE
      • AI / 機器學習
      • AI IP系列
    • CADENCE雲端方案
    • VIEW ALL PRODUCTS
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        • 先進製程
        • Arm-Based方案
        • Cloud Solutions
        • 低功耗方案
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        • Photonics
        • RF / Microwave
      • Industries
        • 5G 系統
        • 航太與國防
        • 車用方案
        • AI / 機器學習
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        • 3D-IC 設計
        • 先進製程
        • Arm-Based方案
        • Cloud Solutions
        • 低功耗方案
        • 混合訊號
        • Photonics
        • RF / Microwave
      • Industries
        • 5G 系統
        • 航太與國防
        • 車用方案
        • AI / 機器學習
      • Technologies
        • 3D-IC 設計
        • 先進製程
        • Arm-Based方案
        • Cloud Solutions
        • 低功耗方案
        • 混合訊號
        • Photonics
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      • Support
        • Support Process
        • Online Support
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        • Technical Forums
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        • Custom IC / Analog / RF Design
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        • Support Process
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Circuit Simulation

Block-level, chip-level, and mixed-signal simulation

  • Circuit Simulation

    • Spectre Simulation Platform
    • Spectre X Simulator
    • Spectre Accelerated Parallel Simulator
    • Spectre eXtensive Partitioning Simulator (XPS)
    • Spectre RF Option
    • Spectre AMS Designer

Block-Level Simulation

Cadence® custom simulation technology delivers all the tools required for designing and verifying your analog/mixed-signal blocks. Simulating blocks has evolved since the days of op-amps and comparators. Consider a typical block such as a fractional-N PLL that has more devices than some traditional analog chips. For block-level design, the steady-state analysis provided by the Spectre® platform can be invaluable for evaluating the noise and transfer functions of blocks like dynamic comparators, time-to-digital converters, et cetera. Block-level verification includes long transient simulations to calibrate blocks, for example, VCO calibration. For blocks, transistor-level simulation is used for verification and it may require transient noise analysis to simulate the key parameters like phase noise. 

Chip-Level Simulation

Leveraging custom design abstraction capabilities, Cadence chip-level simulation looks at all the blocks abstracted into a variety of languages combined with transistor-level blocks that converge on a whole design understanding. Cadence chip-level simulation solutions provide the large capacity and high performance required to ensure that a full chip is working as intended, regardless of how the blocks perform in aggregate.

Mixed-Signal Simulation

Today’s system-on-chip (SoC) designs integrate complex analog and digital blocks, requiring thorough testing and analysis of how analog and digital circuits interact and the influence they have on each other. Cadence mixed-signal simulation solution combines the industry-leading digital and analog circuit simulators: XceliumTM and Spectre, to provide designers and verification engineers superior performance and accuracy required for today’s designs.

With the Spectre platform, you have tools with a common infrastructure, advanced simulation database, versatile front-end parser, and a robust device library. Through integration with our Virtuoso®, Allegro®, and InnovusTM solutions, the Spectre tools deliver comprehensive design and verification.

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