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數位設計流程

Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

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客製IC/類比/RF設計

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系統設計與驗證

Offering a full verification flow to our customers and partners that delivers the highest verification throughput in the industry

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  • 技術產品
    • DESIGN EXCELLENCE
      • 數位設計流程
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
          • Voltus IC Power Integrity Solution
      • 客製IC/類比/RF設計
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • 系統設計與驗證
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
      • IP
        • PRODUCT CATEGORIES
          • Denali Memory Interface and Storage IP
          • 112G/56G SerDes
          • PCIe and CXL
          • Tensilica Processor IP
          • Chiplet and D2D
          • Interface IP
        • RESOURCES
          • Discover PCIe
      • IC封裝設計與分析
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • 系統分析
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • 嵌入式軟體
      • PCB設計與分析
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
      • Computational Fluid Dynamics
    • PERVASIVE INTELLIGENCE
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      • AI IP系列
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        • 低功耗方案
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      • Industries
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        • 航太與國防
        • 車用方案
        • Hyperscale Computing
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        • 3D-IC 設計
        • 先進製程
        • AI / 機器學習
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        • Computational Fluid Dynamics
        • Functional Safety
        • 低功耗方案
        • 混合訊號
        • Photonics
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      • Industries
        • 5G 系統
        • 航太與國防
        • 車用方案
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        • 先進製程
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Virtuoso ADE Verifier

Analog specification verification cockpit

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Key Benefits

 
  • Enables verification of analog electrical circuits
  • Provides overall views into a range of important design parameters
  • Keeps high-level design requirements in line with low-level, specification-driven tests
  • TÜV SÜD “Fit for Purpose – TCL1” certified to meet ISO 26262 automotive functional safety requirements

Cadence® Virtuoso® ADE Verifier is designed to provide a global view of circuit status. Part of the Virtuoso ADE product suite, the Virtuoso ADE Verifier works in conjunction with Virtuoso ADE Assembler and Virtuoso ADE Explorer, enabling tests created in those environments to be linked to the highest level design requirements.

Virtuoso ADE Verifier links high-level requirements such as power consumption, gain, and bandwidth to the individual tests that are being created for specification measurement.

Virtuoso ADE Verifier can link together a group of specification measurement tests across multiple designers or locations and provide the pass / fail status in one easy-to-read window. The Virtuoso ADE Verifier can also quickly identify requirements that have no assigned measurements, and offer visual clues if too few tests are linked to a particular measurement.

Planning flow for analog design

Virtuoso ADE Verifier allows you to test designs to ensure they meet compliance with your standards. The tool allows the specification of critical-path circuit blocks and assures all blocks in a design meet this criteria. Typically the design goals are defined early in the project’s cycle and can then distributed to individual engineers for documentation and testing. Virtuoso ADE Verifier ties back the results to the initial design specification, allowing early identification of possible problems in specific circuits.

Integration flow for analog design

Virtuoso ADE Verifier can create a high-level specification hierarchy after individual tests have already been created. You can use this to your advantage when the design is divided among individual engineers working outside of the Virtuoso platform. Virtuoso ADE Verifier brings all the parts back together in a fully integrated cockpit and makes it easy to see if tests are out-of-date, missing, or are in conflict with the design goals.

Job monitoring

Virtuoso ADE Verifier can run simulation jobs from within the GUI or using command-line scripting. These simulations can be launched from a job monitor window showing test progress, and can inform the architect about any failures within the run that need further investigation.

Integration with MathWorks MATLAB

The integration with MathWorks MATLAB enables you to accelerate processing of large data sets when verifying custom, RF, and mixed-signal designs.

  • Seamlessly share data between the platforms allowing for data mining and efficient analysis improving time to market
  • Solve complex data calculations using expert coding knowledge and low-level APIs

Automotive TCL1 Certified for ISO 26262

The industry’s first analog/mixed-signal design implementation and verification flow to achieve “Fit for Purpose - Tool Confidence Level 1 (TCL1)” certification enables you to meet stringent ISO 26262 automotive safety requirements. The flow brings transistor-level designs from creation and simulation through physical implementation and verification using the Virtuoso ADE Product Suite and the Spectre® Circuit Simulation Platform. The Virtuoso ADE Verifier provides design engineers with an integrated means to validate the safety specifications against individual circuit specifications for design confidence. For information on the safety manuals, Tool Confidence Analysis (TCA) documents, and compliance reports from TÜV SÜD, download the Functional Safety Documentation Kits through Cadence Online Support.

 

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  • Related Products

    • Virtuoso ADE Explorer
    • Virtuoso ADE Assembler
    • Virtuoso Variation Option
  • Related Info

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News ReleasesVIEW ALL
  • Cadence to Acquire AWR Corporation from National Instruments to Accelerate System Innovation for 5G RF Communications 12/02/2019

  • Cadence and National Instruments Enter into Strategic Alliance Agreement to Enhance Electronic System Innovation 12/02/2019

  • Cadence Expands Virtuoso Platform with Enhanced System Design, Advanced Node Support down to 5nm, and Simulation-Driven Layout 04/10/2018

  • Cadence Achieves TÜV SÜD’s First Comprehensive “Fit for Purpose - TCL1” Certification in Support of Automotive ISO 26262 Standard 10/11/2017

  • Cadence Tools and Flows Achieve Production-Ready Certification for TSMC’s 12FFC Process 09/11/2017

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