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CADENCE雲端方案

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數位設計流程

Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

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Cadence® custom, analog, and RF design solutions can help you save time by automating many routine tasks, from block-level and mixed-signal simulation to routing and library characterization.

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  • 技術產品
    • DESIGN EXCELLENCE
      • 數位設計流程
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • 客製IC/類比/RF設計
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Virtuoso RF Solution
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus IC Power Integrity Solution
          • RESOURCES
          • Flows
      • 系統設計與驗證
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Emulation
          • Formal and Static Verification
          • FPGA-Based Prototyping
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
          • Palladium Z1 Enterprise Emulation Platform
          • Protium X1 Enterprise Prototyping Platform
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • Interface IP
          • Denali Memory IP
          • Tensilica Processor IP
          • Analog IP
          • System / Peripherals IP
          • Verification IP
      • IC封裝設計與分析
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • 系統分析
        • PRODUCT CATEGORIES
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Sigrity Advanced SI
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          • RESOURCES
          • System Analysis Resources Hub
      • 嵌入式軟體
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        • PRODUCT CATEGORIES
          • Design Authoring
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          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • What's New in Sigrity
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
    • PERVASIVE INTELLIGENCE
      • AI / 機器學習
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Virtuoso ADE Product Suite

The new sound of analog design

Read Analog Verification White Paper Read ADVANCED-NODE White Paper
  • Overview
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Key Benefits

  • Circuit exploration of analog, mixed-signal, and RFIC designs made easy
  • Extensive design exploration, simulation, and verification
  • Analog specification-verification cockpit
  • A new level of statistical analysis for high-yield and advanced-node designs
  • TÜV SÜD “Fit for Purpose – TCL1” certified to meet ISO 26262 automotive functional safety requirements

With the emergence of new ISO standards, advanced-node designs, and system design requirements, analog engineers are experiencing difficulty maximizing productivity and predictability while meeting aggressive time-to-market deadlines. The Cadence® Virtuoso® ADE product suite offers unparalleled performance and ease-of-use features that set the new standard for quality custom design, analysis, and verification.

The new Virtuoso ADE product suite enables designers to fully explore, analyze, and verify a design against design goals so that they can maintain design intent throughout the design cycle. As the industry’s leading solution for analog simulation control and management, the Virtuoso ADE product suite allows you to flexibly select the product(s) that best support your design goals as you move through the design flow.

Virtuoso ADE Explorer

The Virtuoso ADE Explorer allows you to more easily explore the initial stages of your design with:

  • Spectre® checks supported for detecting and reporting circuit problems during simulation
  • Real-time tuning for fast and accurate pinpointing of your design specifications
  • Pass/fail datasheets
  • Complete corners and Monte Carlo statistical environment for detecting and fixing variation problems before they sink your circuit
Virtuoso ADE Assembler

Using the Virtuoso ADE Assembler, analyze the various conditions of your circuit with an environment that approaches design and analysis from a specification-driven point of view:

  • Quickly test your circuits’ multiple specifications across corners, multiple stimulus testbenches, and statistical variance
  • Added mini-run plans easily create conditional and dependent simulations
  • Built-in advanced statistical features such as worst-case corner development
  • Balance your conflicting design specifications by using advanced optimization technology
  • Extensive design checks can be managed in your design to find faulty nets and devices quickly
  • Verify that your assumptions about critical paths in your design are valid by analyzing partial layout and routing parasitics
  • Optional Virtuoso Variation Option for customers needing to do advanced-node statistics (16nm and below), statistical sensitivity, and high-yield estimation of greater than 3 sigma
Virtuoso ADE Verifier

Get a global view of the circuit status with the Virtuoso ADE Verifier, and easily verify that all the moving pieces of the analog design are contributing to the overall design specifications set by your chip architect. Manual attempts to do this work often lead to mistakes since there is a disconnect between those methods and the design software. This problem does not exist anymore. Now you can:

  • Link analog tests across multiple designers within a company to the highest level specifications of the circuit and view that data in a single, easy-to-use cockpit
  • View test pass/fail results across an entire design team
  • Updates are automatically reflected in the cockpit
  • Use regression testing to build a bridge to the digital world in support of mixed-signal verification
Virtuoso Variation Option

Use the Virtuoso Variation Option to discover areas where the variance of your design could ruin your results:

  • Simple-to-use, task-driven user interface minimizes set-up time
  • Fast Monte Carlo analysis employs high-performance sampling methods to efficiently verify yield or create corners, with additional speed-up for FinFETs
  • High-yield estimation lets you efficiently analyze the 5- or 6-sigma boundaries of your design
  • One-button click to create worst-case 3-sigma corners
  • Statistically based mismatch and sensitivity analyses

Integration with MathWorks MATLAB

The integration with MathWorks MATLAB enables you to accelerate processing of large data sets when verifying custom, RF, and mixed-signal designs:

  • Seamlessly share data between the platforms allowing for data mining and efficient analysis improving time to market
  • Solve complex data calculations using expert coding knowledge and low-level APIs

Automotive TCL1 Certified for ISO 26262

The industry’s first analog/mixed-signal design implementation and verification flow to achieve “Fit for Purpose - Tool Confidence Level 1 (TCL1)” certification enables you to meet stringent ISO 26262 automotive safety requirements. The flow brings transistor-level designs from creation and simulation through physical implementation and verification using the Virtuoso ADE Product Suite and the Spectre Circuit Simulation Platform. The Virtuoso ADE Verifier provides design engineers with an integrated means to validate the safety specifications against individual circuit specifications for design confidence. For information on the safety manuals, Tool Confidence Analysis (TCA) documents, and compliance reports from TÜV SÜD, download the Functional Safety Documentation Kits through Cadence Online Support.

Virtuoso ADE Product Suite

Contact Us

Get a breakdown of key product features in the Virtuoso ADE Product Suite

  • Related Products

    • Virtuoso ADE Explorer
    • Virtuoso ADE Assembler
    • Virtuoso Variation Option
    • Virtuoso ADE Verifier
    • Virtuoso Visualization and Analysis
Resource Library

Press Releases (24)

  • GLOBALFOUNDRIES Collaborates with Cadence on Availability of Mixed-Signal OpenAccess PDK for 22FDX Platform to Enable Advanced Mixed-Signal and mmWave Design
  • Cadence Digital and Custom Flows Achieve Certification for TSMC N3 Process
  • Cadence Achieves Digital and Custom/Analog EDA Flow Certification for TSMC N6 and N5 Process Technologies
  • Cadence to Acquire AWR Corporation from National Instruments to Accelerate System Innovation for 5G RF Communications
  • Cadence and National Instruments Enter into Strategic Alliance Agreement to Enhance Electronic System Innovation
  • Cadence Automotive Reference Flow Certified by Samsung Foundry for Advanced-Node Design Creation
  • Cadence Digital and Signoff Full Flow and Custom/Analog Tools Certified for TSMC N6 and N5/N5P Process Technologies
  • Cadence Introduces the Spectre X Simulator, a Massively Parallel Circuit Simulator Delivering Up to 10X Faster Simulation with the Same Golden Accuracy
  • Cadence Custom/AMS Flow Certified on Samsung 7LPP Process Technology
  • Cadence Expands Virtuoso Platform with Enhanced System Design, Advanced Node Support down to 5nm, and Simulation-Driven Layout
  • Cadence Achieves TÜV SÜD’s First Comprehensive “Fit for Purpose - TCL1” Certification in Support of Automotive ISO 26262 Standard
  • Cadence Tools and Flows Achieve Production-Ready Certification for TSMC’s 12FFC Process
  • Cadence Collaborates with TSMC to Advance 7nm FinFET Plus Design Innovation
  • Cadence Custom/Analog and Full-Flow Digital and Signoff Tools Enabled for GLOBALFOUNDRIES 7LP Process Node
  • Cadence Digital, Signoff and Custom/Analog Tools Enabled on Samsung’s 7LPP and 8LPP Process Technologies
  • Cadence and MathWorks Announce New Integration to Accelerate Data Mining and Analytics
  • Cadence and MathWorks Provide System-Level Simulation Solutions for Mixed-Signal IoT and Automotive Applications
  • Cadence Unveils Next-Generation Virtuoso Platform Featuring Advanced Analog Verification Technologies and 10X Performance Improvements Across Platform
  • Silicon Labs Significantly Reduces Design Time Using the Cadence Mixed-Signal Low-Power Flow
  • Cadence Collaborates with Lumerical and PhoeniX Software to Offer Virtuoso Platform-Based Design Flow for Electronic /Photonic ICs
  • Cadence Unveils Virtuoso Advanced-Node Platform for 10nm Processes
  • Cadence and Intel Collaborate to Release 14nm Library Characterization Reference Flow for Customers of Intel Custom Foundry
  • Cadence Introduces New Mixed-signal and Radio Frequency Capabilities to Address Wireless Design Challenges
  • Cadence Announces New OrCAD Technology to Help Shorten PCB Design Cycles

Presentation (3)

  • Circuit Exploration of Designs Made Easy and Efficient!
  • New Virtuoso Design Platform
  • Speed Up Your Mixed-Signal Verification with Spectre X Simulator

Application Note (1)

  • Multi-Chip Module Design, Verification, and Yield Optimization Using AWR Software

Datasheet (4)

  • Virtuoso ADE Explorer Datasheet
  • Virtuoso ADE Verifier Datasheet
  • Virtuoso Variation Option Datasheet
  • Virtuoso ADE Assembler Datasheet

White Paper (2)

  • Accelerating Monte Carlo Analysis at Advanced Nodes White Paper
  • Plan-Based Analog Verification Methodology White Paper
VIEW ALL
Videos

Design and Verification of Mixed-Signal Systems with MathWorks and Cadence Tools

Accelerate Data Set Processing to Verify Custom and Mixed-Signal Designs

Getting the Most Out of Your Custom Waveforms

Meeting the Challenges of Chip Design Using the Virtuoso Suite

Looking for Efficiency While Leveraging the MathWorks and Cadence Alliance

Virtuoso ADE Explorer, Assembler, and Verifier- hear what people are saying about training

STMicroelectronics – New flow for Analog Top Level Design

Introducing New Integration with MathWorks

Extending the Power of MathWorks MATLAB Inside the Virtuoso ADE Suite

Combined MathWorks and Cadence Design Flow for Analog/Mixed-Signal IC Development

Celebrating 25 Years of Virtuoso Innovation

Verification Made Easy: Learn How to Avoid Mistakes with Virtuoso ADE Verifier

The New Sound of Analog Design: Simplify Design Verification with Virtuoso ADE Product Suite

Easily Explore and Analyze Your Design with Virtuoso ADE Product Suite

News ReleasesVIEW ALL
  • GLOBALFOUNDRIES Collaborates with Cadence on Availability of Mixed-Signal OpenAccess PDK for 22FDX Platform to Enable Advanced Mixed-Signal and mmWave Design 09/24/2020

  • Cadence Digital and Custom Flows Achieve Certification for TSMC N3 Process 08/25/2020

  • Cadence Achieves Digital and Custom/Analog EDA Flow Certification for TSMC N6 and N5 Process Technologies 06/02/2020

  • Cadence to Acquire AWR Corporation from National Instruments to Accelerate System Innovation for 5G RF Communications 12/02/2019

  • Cadence and National Instruments Enter into Strategic Alliance Agreement to Enhance Electronic System Innovation 12/02/2019

Blogs VIEW ALL
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