- Design capacity of up to 100K cells
- Silicon-accurate timing and power signoff with signal integrity analysis
- Integration with Innovus™ Implementation System and Virtuoso® Layout Suite
A small-scale signoff solution that fills an important void, the Cadence® Virtuoso Digital Signoff Solution delivers capabilities for both power and timing analysis. Right-size packaging allows you to migrate away from implementation signoff compromises.
As mixed-signal designs move to more advanced process nodes, there’s a growing need for a signoff-quality tool. Signal integrity and waveform effects require signoff-quality analysis. Until now, your options have been limited—you’ve had to do signoff with implementation tools (which doesn’t result in signoff-quality results), or you’ve had to do signoff with a full signoff seat (which can be a bigger investment than you want).
Our Virtuoso Digital Signoff Solution fills the gap for power and timing analysis. The solution consists of two flavors: Virtuoso Digital Signoff Timing Solution and Virtuoso Digital Signoff Power Solution. Both support advanced-node processes, including FinFET nodes.
Better Timing Convergence
Based on the Cadence Tempus™ Timing Signoff Solution, Virtuoso Digital Signoff Timing Solution provides enhanced timing convergence throughout the design flow via tight coupling with the design implementation environment. With the solution, you get:
- Static timing analysis with delay calculation and signal integrity effects
- Noise glitch analysis
- Distributed/concurrent multi-mode, multi-corner (MMMC) optimization
- Cross-probing of timing paths from timing report to Virtuoso Layout Suite layout editor
- Interactive engineering change order (ECO)
- SDC lint checks
- SDC policy checks, including hierarchical checks
- SDC integration
Faster Power Signoff
Based on the Cadence Voltus™ IC Power Integrity Solution, the Virtuoso Digital Signoff Power Solution provides accurate and fast analysis and optimization technologies for debugging, verifying, and fixing IC chip power consumption, IR drop, and electromigration constraints and violations. The solution delivers:
- Static power and EMIR analysis
- Dynamic power and EMIR analysis
- Advanced analysis including advanced FinFET nodes, FD-SOI nodes, full-chip resistance analysis, and ESD