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  • 技術產品
    • DESIGN EXCELLENCE
      • 數位設計流程
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Genus Synthesis Solution
          • Conformal Smart LEC
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
      • 客製IC/類比/RF設計
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Virtuoso RF Solution
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus IC Power Integrity Solution
          • RESOURCES
          • Flows
      • 系統設計與驗證
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Emulation
          • Formal and Static Verification
          • FPGA-Based Prototyping
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • JasperGold Formal Verification Platform
          • Xcelium Logic Simulation
          • Palladium Z1 Enterprise Emulation Platform
          • Protium X1 Enterprise Prototyping Platform
          • System VIP
          • RESOURCES
          • Flows
      • IP
        • PRODUCT CATEGORIES
          • Interface IP
          • Denali Memory IP
          • Tensilica Processor IP
          • Analog IP
          • System / Peripherals IP
          • Verification IP
      • IC封裝設計與分析
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • 系統分析
        • PRODUCT CATEGORIES
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Sigrity Advanced SI
          • Sigrity Advanced PI
          • RESOURCES
          • System Analysis Resources Hub
      • 嵌入式軟體
      • PCB設計與分析
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • What's New in Sigrity
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
    • PERVASIVE INTELLIGENCE
      • AI / 機器學習
      • AI IP系列
    • CADENCE雲端方案
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Low-Power Solution

A design-to-signoff methodology that is comprehensive, interoperable, and proven

  • Low-Power Solution
  • Power-Aware Verification
  • Power-Aware Implementation

Key Benefits

  • Comprehensive solution for low power including architecture optimization, power estimation and analysis, functional verification, implementation and signoff, and IP for digital and mixed-signal designs at both chip and system level
  • Support for both industry-standard power intent formats (CPF and IEEE 1801), enabling customers to adopt the design flow of their choice
  • Production proven on thousands of designs mitigating risk of re-spins, reducing product development time and costs

With the emergence of wearables, smart appliances for home, industrial automation, automotive electronics, and big data processing, low-power design is no longer confined to the mobile device end markets. Power management touches every aspect of the design flow, from the architectural stage to chip and system signoff. Consequently, EDA tools have to take a holistic approach to low-power design.

The Cadence® low-power solution considers power at every step of the design flow, from architecture to functional verification, analysis, implementation, and signoff.

High-level synthesis (HLS) methodology users benefit from the power-aware architectural/micro-architectural choices available from a very high-level description of the design. This supports making the right trade-offs for power, performance, and area (PPA) at the earliest stages of the design when it matters the most. 

Once the RTL and power intent are available for analysis, the Cadence solution helps perform a sanity check of the power intent itself. This prevents unexpected surprises as the designer progresses through the low-power flow. The Cadence solution supports both the IEEE 1801 and CPF industry-standard formats for power intent. Simulation, emulation, and formal verification tools from Cadence are power-aware and verify the design interactions between functional and power modes in which the design is meant to operate. This helps to eliminate hard-to-find design or power intent bugs that could potentially cause chip and system failures in the field.

All aspects of implementation consider the power intent and make trade-offs and optimizations for leakage and dynamic power to deliver a low-power design with high Quality of Results (QoR). At every stage of implementation, the Cadence solution helps verify that the low-power design is compliant with the specified power intent. Signoff tools are power intent-driven as well, ensuring that the power intent has been implemented correctly to avoid re-spins and product delays and reduce product costs.

The Cadence low-power solution has also built links between the chip and system level to verify that the power integrity of the entire system is achieved in the context of the chip, board, and package.

Cadence has enabled the low-power flow for mixed-signal designs as well. Intellectual property (IP) in the form of embedded customizable processor cores and interface IP optimized for power consumption is available from Cadence.

Finally, the Cadence low-power solution has been used in production in thousands of designs.

  • Related Products

    • Stratus High-Level Synthesis
    • Genus Synthesis Solution
    • Innovus Implementation System
    • Tempus Timing Signoff Solution
    • Voltus IC Power Integrity Solution
    • Conformal Low Power
    • Joules RTL Power Solution
    • Perspec System Verifier
    • vManager Verification Management
    • Palladium Dynamic Power Analysis
    • Modus Test Solution
    • Conformal Low Power
    • JasperGold Low-Power Verification App
    • Xcelium Logic Simulator
    • Palladium Z1 Enterprise Emulation System
    • Protium S1 FPGA-Based Prototyping Platform
    • Palladium Dynamic Power Analysis
    • Indago Debug Analyzer App
Resource Library

White Paper (2)

  • A Better Tool for Functional Verification of Low-Power Designs with IEEE 1801 UPF White Paper
  • Building Energy-Efficient ICs from the Ground Up White Paper

Press Releases (1)

  • Silicon Labs Significantly Reduces Design Time Using the Cadence Mixed-Signal Low-Power Flow
VIEW ALL
Videos

Closing Gaps in Mixed-Signal Power Implementation Using a Consistent Power Intent

Developing 4G Wireless Designs with Cadence CPF-Driven Low-Power Solution

Accurate Low Power verification on a Complex Low Power Design using CLP

Freeescale Semiconductor - Cadence Low-Power Solution for Kinetis SoC

Lowering Leakage Power in ARM Cortex-A17 Processor-based SoCs at GLOBALFOUNDRIES

Low-Power Summit ARM Sathya Subramanian

News ReleasesVIEW ALL
  • Cadence Completes Acquisition of NUMECA 02/24/2021

  • Cadence's Lip-Bu Tan to Present at Morgan Stanley Conference 02/23/2021

  • Cadence Reports Fourth Quarter and Fiscal Year 2020 Financial Results 02/22/2021

  • Cadence Announces $5M Endowment at Massachusetts Institute of Technology 02/02/2021

  • Cadence併購計算流體力學公司NUMECA擴展系統分析能力 01/22/2021

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