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Cadence® digital design and signoff solutions provide a fast path to design closure and better predictability, helping you meet your power, performance, and area (PPA) targets.

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系統設計與驗證

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  • 技術產品
    • DESIGN EXCELLENCE
      • 數位設計流程
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
          • Voltus IC Power Integrity Solution
      • 客製IC/類比/RF設計
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • 系統設計與驗證
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
      • IP
        • PRODUCT CATEGORIES
          • Denali Memory Interface and Storage IP
          • 112G/56G SerDes
          • PCIe and CXL
          • Tensilica Processor IP
          • Chiplet and D2D
          • Interface IP
        • RESOURCES
          • Discover PCIe
      • IC封裝設計與分析
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
    • SYSTEM INNOVATION
      • 系統分析
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • Electromagnetic Solutions
          • RF / Microwave Design
          • Signal and Power Integrity
          • Thermal Solutions
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • 嵌入式軟體
      • PCB設計與分析
        • PRODUCT CATEGORIES
          • Design Authoring
          • PCB Layout
          • Library and Design Data Management
          • Analog/Mixed-Signal Simulation
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • RF / Microwave Design
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
          • Allegro PCB Designer
          • RESOURCES
          • What's New in Allegro
          • Advanced PCB Design & Analysis Resources Hub
          • Flows
      • Computational Fluid Dynamics
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      • Industries
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        • 車用方案
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        • 3D-IC 設計
        • 先進製程
        • AI / 機器學習
        • Arm-Based方案
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        • Computational Fluid Dynamics
        • Functional Safety
        • 低功耗方案
        • 混合訊號
        • Photonics
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      • Industries
        • 5G 系統
        • 航太與國防
        • 車用方案
        • Hyperscale Computing
      • Technologies
        • 3D-IC 設計
        • 先進製程
        • AI / 機器學習
        • Arm-Based方案
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Custom/Analog Advanced Node

Innovative capabilities for custom/analog designs at 20nm and below 

  • Advanced-Node Solutions
  • Custom/Analog Advanced Node
  • Digital Advanced Node

Key Benefits

  • Increases quality of silicon: Re-engineered from the ground up to support the most aggressive advanced-node processes 
  • Boosts productivity: New design methodologies along with the introduction of targeted automation techniques enhance productivity by up to 5X versus traditional design tools and flows
  • Avoids costly respins: Close collaboration with leading foundries provides capabilities in the Virtuoso advanced-node platform that let you predict and manage process variability up front in the design flow
  • Industry leader in advanced-node custom design: The Virtuoso advanced-node platform supports and is certified by all major foundries for advanced technologies from 20nm down to 3nm

Innovative Capabilities for Custom/Analog Designs at 20nm and Below

System-on-chip (SoC) solutions must have the right mix of features, functionality, and performance to justify designing at advanced nodes. But the key challenges for custom/analog designers arise from the complexity of manufacturing. The Cadence® Virtuoso® advanced-node platform's innovative capabilities enable designers to take full advantage of the silicon.

Advanced Node Solution
Density gradient effect avoidance

Unique Design Challenges at 20nm, 16nm, 10nm, 7nm, 5nm, and 3nm Advanced Process Nodes

What makes designing at 20nm/16nm/14nm/10nm/7nm/5nm/3nm advanced nodes unique is the deep, complex interdependency of manufacturing and variability, on top of increasing power and performance specifications. 

Concerns include:

  • Multiple-patterning technology (MPT) and color-aware physical design, including double, triple, quadruple, and penta-patterning
  • Layout-dependent effects (LDE) and density-gradient effects (DGE), in which the layout context—what is placed near to a device—can impact device performance by as much as 30%
  • Sophisticated color-aware custom routing
  • Exponentially increasing physical design rules
  • Device variation and sensitivity
  • New transistor types (e.g., FinFETs)
Image showing Cadence Advanced Node Platform displaying graph of EM violations
EM violation avoidance

Why Design with Virtuoso Advanced-Node Platform

The Virtuoso advanced-node platform improves individual point tools to handle these challenges, as well as enables new design methodologies that allow for rapid layout prototyping, in-design signoff, and close collaboration between schematic and layout designers—essential to designing efficiently at advanced-process nodes. 

The latest release of the Virtuoso advanced-node platform includes:

  • Robust support for FinFET-based designs, requiring MPT to manage device variability and sensitivity on the circuit design
  • Many enhanced interactive and automated capabilities to support a structured layout methodology with features such as core editing commands, interactive wire editor, module generators (ModGens), fully automated custom routing, and assisted placement, all design rules checking (DRC) and coloring correct
  • Unique and close integration with the Virtuoso physical verification system (PVS), enabling signoff verification support for both DRC and coloring decomposition within the Virtuoso Layout Suite
Advanced Node Solution
Multiple-patterning support and color-aware physical design
Advanced Node Solution
In-design design rule checking
  • Related Products

    • Virtuoso Layout Suite EAD
    • Virtuoso Space-Based Router
    • Liberate Characterization Solution
    • Spectre X Simulator
    • Liberate Variety Statistical Characterization
    • Virtuoso Variation Option
Resource Library

Press Releases (20)

  • Cadence RFIC Solutions Support TSMC N6RF Design Reference Flow | Cadence
  • Cadence Joins Intel Foundry Services Ecosystem Alliance to Advance Chip Design Innovation | Cadence
  • Cadence Wins Four 2021 TSMC OIP Partner of the Year Awards, Featuring Key Advancements in 3DFabric Design and Cloud-Based Solutions | Cadence
  • Cadence and Samsung Accelerate 3nm Mixed-Signal Silicon | Cadence
  • Cadence榮獲2020年四項台積電開放創新平台夥伴大獎 | Cadence
  • Cadence Digital and Custom Flows Achieve Certification for TSMC N3 Process | Cadence
  • Cadence Achieves Digital and Custom/Analog EDA Flow Certification for TSMC N6 and N5 Process Technologies | Cadence
  • Cadence and National Instruments Enter into Strategic Alliance Agreement to Enhance Electronic System Innovation | Cadence
  • Cadence Presented with Four 2019 TSMC Partner of the Year Awards | Cadence
  • Cadence Digital and Signoff Full Flow and Custom/Analog Tools Certified for TSMC N6 and N5/N5P Process Technologies | Cadence
  • Cadence Collaborates with TSMC to Accelerate 5nm FinFET Innovation, Enabling Next-Generation SoC Production Design | Cadence
  • Cadence Recognized with Four 2018 TSMC Partner of the Year Awards | Cadence
  • Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies to Facilitate Mobile and HPC Design Creation | Cadence
  • Cadence Collaborates with TSMC to Advance 5nm and 7nm+ Mobile and HPC Design Innovation | Cadence
  • Cadence Expands Virtuoso Platform with Enhanced System Design, Advanced Node Support down to 5nm, and Simulation-Driven Layout | Cadence
  • Cadence Custom/Analog and Full-Flow Digital and Signoff Tools Enabled for GLOBALFOUNDRIES 7LP Process Node | Cadence
  • Cadence Digital, Signoff and Custom/Analog Tools Enabled on Samsung’s 7LPP and 8LPP Process Technologies | Cadence
  • Cadence Unveils Expanded Virtuoso Advanced-Node Platform for 7nm Processes | Cadence
  • Cadence and TSMC Advance 7nm FinFET Designs for Mobile and HPC Platforms | Cadence
  • Cadence Unveils Virtuoso Advanced-Node Platform for 10nm Processes | Cadence

Presentation (1)

  • New Virtuoso Design Platform
VIEW ALL
Videos

Avoid Density Gradient Effects in 16FF+ Designs with Virtuoso Layout Suite GXL ModGens

Virtuoso IPVS for Advanced Node Design

Enhancing Design Productivity at STMicroelectronics with Virtuoso Custom/Analog Flow

Custom Layout Methodologies with Virtuoso Advanced Node

Virtuoso Technology for Advanced Process Nodes

Advanced Node Multi-Patterning Technologies within Virtuoso Environment

Advanced Methodologies to Accelerate Your Custom Layout

Toshiba Electronic Device Solutions Overcomes Complexities of Advanced-Node Designs

Advanced Node Layout Methodology For Memories

Why a Row-Based Methodology is Required for Sub-10nm Custom Layout

Improved Analog Layout Productivity Using ModGen Template-Driven Layout Reuse Methodology in Virtuoso Environment

News ReleasesVIEW ALL
  • Cadence RFIC Solutions Support TSMC N6RF Design Reference Flow 06/16/2022

  • Cadence Joins Intel Foundry Services Ecosystem Alliance to Advance Chip Design Innovation 02/07/2022

  • Cadence Wins Four 2021 TSMC OIP Partner of the Year Awards, Featuring Key Advancements in 3DFabric Design and Cloud-Based Solutions 11/12/2021

  • Cadence and Samsung Accelerate 3nm Mixed-Signal Silicon 09/08/2021

  • Cadence榮獲2020年四項台積電開放創新平台夥伴大獎 11/03/2020

Blogs VIEW ALL
Fortune 100 Best Companies to Work for 2022

A Great Place to Do Great Work!

Eighth year on the FORTUNE 100 list

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