Key Benefits
- Increases quality of silicon: Re-engineered from the ground up to support the most aggressive advanced-node processes
- Boosts productivity: New design methodologies along with the introduction of targeted automation techniques enhance productivity by up to 5X versus traditional design tools and flows
- Avoids costly respins: Close collaboration with leading foundries provides capabilities in the Virtuoso advanced-node platform that let you predict and manage process variability up front in the design flow
- Industry leader in advanced-node custom design: The Virtuoso advanced-node platform supports and is certified by all major foundries for advanced technologies from 20nm down to 3nm
Innovative Capabilities for Custom/Analog Designs at 20nm and Below
System-on-chip (SoC) solutions must have the right mix of features, functionality, and performance to justify designing at advanced nodes. But the key challenges for custom/analog designers arise from the complexity of manufacturing. The Cadence® Virtuoso® advanced-node platform's innovative capabilities enable designers to take full advantage of the silicon.
Density gradient effect avoidance
Unique Design Challenges at 20nm, 16nm, 10nm, 7nm, 5nm, and 3nm Advanced Process Nodes
What makes designing at 20nm/16nm/14nm/10nm/7nm/5nm/3nm advanced nodes unique is the deep, complex interdependency of manufacturing and variability, on top of increasing power and performance specifications.
Concerns include:
- Multiple-patterning technology (MPT) and color-aware physical design, including double, triple, quadruple, and penta-patterning
- Layout-dependent effects (LDE) and density-gradient effects (DGE), in which the layout context—what is placed near to a device—can impact device performance by as much as 30%
- Sophisticated color-aware custom routing
- Exponentially increasing physical design rules
- Device variation and sensitivity
- New transistor types (e.g., FinFETs)
EM violation avoidance
Why Design with Virtuoso Advanced-Node Platform
The Virtuoso advanced-node platform improves individual point tools to handle these challenges, as well as enables new design methodologies that allow for rapid layout prototyping, in-design signoff, and close collaboration between schematic and layout designers—essential to designing efficiently at advanced-process nodes.
The latest release of the Virtuoso advanced-node platform includes:
- Robust support for FinFET-based designs, requiring MPT to manage device variability and sensitivity on the circuit design
- Many enhanced interactive and automated capabilities to support a structured layout methodology with features such as core editing commands, interactive wire editor, module generators (ModGens), fully automated custom routing, and assisted placement, all design rules checking (DRC) and coloring correct
- Unique and close integration with the Virtuoso physical verification system (PVS), enabling signoff verification support for both DRC and coloring decomposition within the Virtuoso Layout Suite
Multiple-patterning support and color-aware physical design
In-design design rule checking
Resource Library
Press Releases (20)
- Cadence RFIC Solutions Support TSMC N6RF Design Reference Flow | Cadence
- Cadence Joins Intel Foundry Services Ecosystem Alliance to Advance Chip Design Innovation | Cadence
- Cadence Wins Four 2021 TSMC OIP Partner of the Year Awards, Featuring Key Advancements in 3DFabric Design and Cloud-Based Solutions | Cadence
- Cadence and Samsung Accelerate 3nm Mixed-Signal Silicon | Cadence
- Cadence榮獲2020年四項台積電開放創新平台夥伴大獎 | Cadence
- Cadence Digital and Custom Flows Achieve Certification for TSMC N3 Process | Cadence
- Cadence Achieves Digital and Custom/Analog EDA Flow Certification for TSMC N6 and N5 Process Technologies | Cadence
- Cadence and National Instruments Enter into Strategic Alliance Agreement to Enhance Electronic System Innovation | Cadence
- Cadence Presented with Four 2019 TSMC Partner of the Year Awards | Cadence
- Cadence Digital and Signoff Full Flow and Custom/Analog Tools Certified for TSMC N6 and N5/N5P Process Technologies | Cadence
- Cadence Collaborates with TSMC to Accelerate 5nm FinFET Innovation, Enabling Next-Generation SoC Production Design | Cadence
- Cadence Recognized with Four 2018 TSMC Partner of the Year Awards | Cadence
- Cadence Achieves EDA Certification for TSMC 5nm and 7nm+ FinFET Process Technologies to Facilitate Mobile and HPC Design Creation | Cadence
- Cadence Collaborates with TSMC to Advance 5nm and 7nm+ Mobile and HPC Design Innovation | Cadence
- Cadence Expands Virtuoso Platform with Enhanced System Design, Advanced Node Support down to 5nm, and Simulation-Driven Layout | Cadence
- Cadence Custom/Analog and Full-Flow Digital and Signoff Tools Enabled for GLOBALFOUNDRIES 7LP Process Node | Cadence
- Cadence Digital, Signoff and Custom/Analog Tools Enabled on Samsung’s 7LPP and 8LPP Process Technologies | Cadence
- Cadence Unveils Expanded Virtuoso Advanced-Node Platform for 7nm Processes | Cadence
- Cadence and TSMC Advance 7nm FinFET Designs for Mobile and HPC Platforms | Cadence
- Cadence Unveils Virtuoso Advanced-Node Platform for 10nm Processes | Cadence
Presentation (1)
