Improving Performance of SoCs with Interconnect Workbench and CoreLink System IP

Ziv Binyamini, Corporate VP of Advanced Verification Solutions at Cadence, describes the exciting capabilities of the Xcelium Parallel Simulator and its multi-core and single-core simulators. Productivity enhancements includes code coverage, resiliency refinements around save-restore

上次修改時間: August 22, 2015

持續時間: 3 min