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  • Hsinchu, Taiwan, 22 Jul 2021

Cadence 推出以機器學習為基礎的革命性產品Cerebrus 提供無與倫比的生產力和品質、擴大數位設計領導地位

SAN JOSE, Calif., 22 Jul 2021

重點提示:

  • Cerebrus 使用獨特的機器學習科技,來驅動 Cadence暫存器傳輸級到簽核的實現流程,提升10 倍的生產力以及高達20%的功耗、效能與面積(PPA)優化程度。
  • 採用可重複運行和可移植的強化學習模型進行建構,讓每次使用都能提高效果。
  • 提供比傳統的人工驅動設計更加高效的本地和雲端運算資源管理能力。
  • 改善跨節點和多重終端應用的功耗、效能、面積(PPA)和生產力,該應用層面包括消費者、超大規模運算、5G 通訊、汽車和行動裝置設計等。

全球電子設計創新領導廠商Cadence Design Systems, Inc.(益華電腦)今天宣布推出 Cadence® Cerebrus ™智慧晶片探測工具 (Intelligent Chip Explorer),這是一款以機器學習為技術基礎所開發的新型工具,可實現數位晶片設計自動化和規模化,讓客戶能夠更快速地達到客製化晶片設計的目標。相較於人工操作方式,Cerebrus 和 Cadence暫存器傳輸級到簽核流程(RTL-to-signoff) 的結合,使高階晶片設計人員、電腦輔助設計團隊和矽智財開發者,能提高多達 10 倍的工程生產力,以及優化高達20%的功耗、效能與面積(PPA)。

Cerebrus的問世,不僅成為Cadence眾多數位產品的一員,也讓Cadence 提供業界最先進以機器學習為基礎的數位全流程,其範圍涵蓋合成(synthesis) 、實現(implementation)到簽核(signoff)等。此一新工具可在雲端平台運作,它可利用高度且可擴展的運算資源,快速滿足市場上廣泛多元的設計需求,包括消費性、超大規模運算、5G 通訊、汽車和行動裝置等。有關 Cerebrus 的更多訊息,請點擊  www.cadence.com/go/cerebruspr

Cerebrus 可以為客戶提供下列益處:

  • 強化機器學習效能:快速找到工程師可能不會主動嘗試或探索的流程解決方案,從而提高功耗、效能、面積(PPA)和生產力。
  • 機器學習程序可重複運行:可以讓前一次的設計學習,自動應用在未來的設計工作上,縮短達到更佳產出的時間。
  • 提高生產力:讓單一工程師能夠同時針對多個模塊,進行完整的RTL到GDS流程自動優化,提高全設計團隊的生產力。
  • 大規模分佈式計算:提供可擴展式的就地部署(on-premises)或雲端的設計探索,以加快流程優化。
  • 方便使用的人機介面:強大的操作功能,讓使用者可以進行互動式結果分析與運行管理,獲得晶片設計指標相關的重要見解。

Cadence資深副總裁暨數位與簽核事業群總經理滕晉慶(Chin-Chi Teng)博士指出:「過去,設計團隊無法使用自動化方式,重複運行前次的設計程式,導致每個新項目耗費過多時間在人工學習上,並造成利潤損失。Cerebrus 的問世,標示著機器學習技術所帶動的數位晶片電子設計自動化產業的革新,讓工程團隊可以釋放人力操作,進而有機會在組織中產生更大的影響。隨著產業繼續朝先進節點、設計尺寸和複雜性漸增發展時,Cerebrus 正可以讓設計人員更有效地實現功耗、效能與面積(PPA)的優化目標。」

Cerebrus 是Cadence數位全流程多元產品的一部分,能與既有產品無縫協作,包括 Genus™ 合成解決方案、Innovus™ 設計實現系統、Tempus™ 時序簽核解決方案、Joules™ RTL電源解決方案、Voltus™電源完整性解決方案,以及 Pegasus™ 驗證系統。此無縫協作可以提供客戶快速的設計收斂途徑以及更佳的可預測性。此新工具及其多元的流程應用,將能更完善Cadence智慧系統設計(Intelligent System Design™) 的整體策略,使無所不在的智慧成為卓越設計的基石。客戶的認可

客戶的認可

「為了使採用最新流程節點的新產品效能極大化,我們工程團隊使用的數位實現流程必須不斷更新。自動化設計流程的優化,對於在更高產量需求中完成產品開發,至關重要。Cerebrus 以其創新性的機器學習能力,和 Cadence RTL-to-signoff工具,提供了自動化流程優化和佈局規劃開發,將設計效能提高 10% 以上。在取得這一成功之後,我們將能夠在最新設計項目中,採用此新方法來開發。」

- 瑞薩電子公司共享研發EDA部門數位設計技術部總監Satoshi Shibatani

「隨著三星晶圓代工不斷採用最新的製程節點,效率對我們設計技術協同優化 (DTCO) 計劃至關重要,我們一直在尋找創新方法以在晶片設計實現方面優化 PPA。作為我們與 Cadence 長期合作夥伴關係的一部分,三星晶圓代工多個應用程序中已使用了 Cerebrus 和 Cadence 數位設計流程。我們觀察到,與耗時數月的手動工作相比,一些最關鍵模塊的功耗在短短幾天內降低了8% 以上。此外,我們使用 Cerebrus 進行自動化佈局規劃配電網絡規模調整,這使最終設計時序提高了 50% 以上。由於 Cerebrus 和數位設計實現流程提供了更好的 PPA 和明顯的生產力優化,該解決方案已成為我們 DTCO 計劃寶貴的一部份。」

- 三星晶圓代工設計技術副總裁Sangyun Kim

關於Cadence 益華電腦

Cadence在運算軟體領域擁有超過30年的經驗,已為當今電子設計的領導者。公司以智慧系統設計 (Intelligent System Design) 為核心策略,提供軟體、硬體及半導體IP,協助電子設計從概念走向應用實現Cadence服務全球客戶,從晶片、印刷電路板至整體系統打造尖端與創新的電子產品,以應用於行動、消費性電子、超大型運算、5G通訊、汽車、航太、工業及健康醫療等當今最活躍的市場。Cadence 已連續七年榮獲財星雜誌(FORTUNE)評列「百大最佳職場」之肯定。Learn more at cadence.com.

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