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  • 技術產品
    • DESIGN EXCELLENCE
      • 數位設計流程
        • Logic Equivalence Checking
        • Innovus Implementation and Floorplanning
        • Functional ECO
        • Low-Power Validation
        • Synthesis
        • Power Analysis
        • Constraints and CDC Signoff
        • Silicon Signoff and Verification
        • Library Characterization
        • Test
        • Flows
      • 客製IC/類比/RF設計
        • Circuit Design
        • Circuit Simulation
        • Layout Design
        • Layout Verification
        • Library Characterization
        • RF / Microwave Solutions
        • Flows
      • 系統設計與驗證
        • Debug Analysis
        • Emulation
        • Formal and Static Verification
        • FPGA-Based Prototyping
        • Planning and Management
        • Simulation
        • Software-Driven Verification
        • Verification IP
        • System-Level Verification IP
        • Flows
      • IP
        • Interface IP
        • Denali Memory IP
        • Tensilica Processor IP
        • Analog IP
        • System / Peripherals IP
        • Verification IP
      • IC封裝設計與分析
        • Cross-Platform Co-Design and Analysis
        • IC Package Design
        • SI/PI Analysis
        • SI/PI Analysis Point Tools
        • Flows
    • SYSTEM INNOVATION
      • 系統分析
        • Electromagnetic Solutions
        • RF / Microwave Design
        • Thermal Solutions
        • System Analysis Resources Hub
      • 嵌入式軟體
      • PCB設計與分析
        • Design Authoring
        • PCB Layout
        • Library and Design Data Management
        • Analog/Mixed-Signal Simulation
        • SI/PI Analysis
        • SI/PI Analysis Point Tools
        • What's New in Allegro
        • What's New in Sigrity
        • RF / Microwave Design
        • Flows
        • Advanced PCB Design & Analysis Blog
        • Augmented Reality Lab Tools
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  • 12 Aug 2020

Cadence Delivers Machine Learning-Optimized Xcelium Logic Simulation with up to 5X Faster Regressions

Core engine performance enhancements accelerate verification throughput by reducing simulation cycles with matching coverage on randomized test suites

SAN JOSE, Calif., 12 Aug 2020

Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the Cadence® XceliumTM Logic Simulator has been enhanced with machine learning technology (ML), called Xcelium ML, to increase verification throughput. Using new machine learning technology and core computational software, Xcelium ML enables up to 5X faster verification closure on randomized regressions.

Using computational software and a proprietary machine learning technology that directly interfaces to the simulation kernel, Xcelium ML learns iteratively over an entire simulation regression. It analyzes patterns hidden in the verification environment and guides the Xcelium randomization kernel on subsequent regression runs to achieve matching coverage with reduced simulation cycles.

Cadence’s Xcelium Logic Simulator provides best-in-class core engine performance for SystemVerilog, VHDL, mixed-signal, low power, and x-propagation. It supports both single-core and multi-core simulation, incremental and parallel build, and save/restart with dynamic test reload. The Xcelium Logic Simulator has been deployed by a majority of top semiconductor companies, and a majority of top companies in the hyperscale, automotive and consumer electronics segments.

“Kioxia has effectively utilized Xcelium simulation for a variety of our designs, and it addresses our ever-growing verification needs,” said Kazunari Horikawa, senior manager, Design Technology Innovation Division at Kioxia Corporation. “With the new Xcelium ML, we’ve seen a 4X shorter turnaround time in our fully random regression runs to reach 99% function coverage of original, and plan to use this technology in production designs to shorten the time to market for Kioxia’s business.”

“Xcelium ML is a powerful technology and a great example of the significant opportunity we have to leverage machine learning in verification,” said Paul Cunningham, corporate vice president and general manager of the System & Verification Group at Cadence. “Logic simulation continues to be the workhorse of digital verification, and we are investing heavily in fundamental performance optimizations like Xcelium ML to deliver the highest verification throughput to customers using our flow.”

Xcelium ML is part of the Cadence Verification Suite and supports the company’s Intelligent System DesignTM strategy, enabling pervasive intelligence and faster design closure. For more information on Xcelium ML, please visit http://www.cadence.com/go/XceliumML.

About Cadence

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace, industrial and healthcare. For six years in a row, Fortune magazine has named Cadence one of the 100 Best Companies to Work For. Learn more at cadence.com.

For more information, please contact:

Cadence Newsroom
408-944-7039
newsroom@cadence.com

© 2020 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.

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