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          • Discover PCIe
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  • 13 Oct 2020

Cadence推出全新系統VIP解決方案 將驗證IP推向晶片層級

新方案可為超大規模、車用、行動及消費類晶片的系統級測試台的組裝、執行及分析帶來最高10倍的效率提升

Hsinchu, Taiwan, 14 Oct 2020

全球電子設計創新領導廠商益華電腦(Cadence Design Systems, Inc.)宣佈推出全新Cadence®系統級驗證VIP(Verification IP),可用於自動化系統單晶片(SoC)測試台組裝、匯流排(bus)及CPU流量生成、高速緩衝記憶體一致性驗證、及系統性能瓶頸分析的新工具及庫套件。客戶採用Cadence 系統驗證IP可創建複雜的超大規模、汽車、行動及消費類晶片,可將晶片級驗證效率提高近10倍。

欲知有關Cadence 系統VIP的詳情,請參考www.cadence.com/go/SystemVIPpr。

全新Cadence 系統VIP解決方案,使Cadence在IP級驗證自動化方面,處於市場領導地位,並將其帶入晶片層級。藉由Cadence系統VIP解決方案創建的測試,可跨Cadence模擬、仿真及原型引擎進行轉移,並可擴展到矽後流程啟動。Cadence 系統 VIP包含四個新工具及元件庫:

  • 系統測試台生成器:允許客戶自動生成具複雜記憶體、高速緩衝記憶體、介面及匯流排配置的SoC測試台;
  • 系統流量庫:為使用者提供豐富與可直接嵌入系統VIP測試平台的預先定義測試內容,包括一致性、性能、PCI Express®(或簡稱PCIe®)及NVMe子系統;
  • 系統性能分析器:為記憶體子系統、互連及周邊設備,提供全面的效能分析報告及可視化;
  • 系統驗證計分板:在相關的互連、記憶體及周邊設備間,提供全面的數據及高速緩衝記憶體一致性檢查。

瑞薩電子EDA通用技術開発事業部設計方法部部長浅野 哲也表示:「多年來瑞薩一直使用Cadence VIP,並感謝Cadence在先進SoC驗證技術方面的領導地位。藉由採用新的系統 VIP來補充我們現有的基於Xcelium及Palladium引擎的驗證環境,並改善重複使用和自動化,我們可進一步将SoC驗證過程效率提高10倍,使我們能夠更快地向客戶提供創新的高質量產品。」

Arm 設計服務處長Tran Nguyen表示:「藉由與Cadence的合作,我們可減少複雜SoC的驗證挑戰,特別是I/O周邊,透過使用Cadence系統流量庫和系統性能分析器,Arm能夠將複雜的測試生成過程自動化,從而實現了更快的PCIe整合驗證和效能分析。」

Cadence副總裁暨系統與驗證部門總經理Paul Cunningham:「驗證的挑戰隨著SoC上整合IP模塊的數量及複雜性而成倍增長。我們新的Cadence系統 VIP解決方案將當今最關鍵的人工密集型晶片級驗證任務自動化,可大幅度提高驗證生產力。」

Cadence 系統VIP工具套裝為 Cadence驗證套裝一部分,此產品支持公司的智慧系統策略。Cadence驗證套裝包含核心引擎與智慧驗證技術,可增加驗證生產力與設計品質,滿足廣泛的應用與垂直市場的驗證需求 。

關於 Cadence

Cadence在運算軟體領域擁有超過30年的經驗,已為當今電子設計的領導者。公司以智慧系統設計 (Intelligent System Design) 為核心策略,提供軟體、硬體及半導體IP,協助電子設計從概念走向應用實現。Cadence服務全球客戶,從晶片、印刷電路板至整體系統打造尖端與創新的電子產品,以應用於消費性電子、超大型運算、5G通訊、汽車、航太、工業及健康醫療等當今最活躍的市場。Cadence 已連續六年榮獲財星雜誌(FORTUNE)評列「百大最佳職場」之肯定。詳細Cadence 資訊,請見  www.cadence.com.

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