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  • 技術產品
    • DESIGN EXCELLENCE
      • 數位設計流程
        • PRODUCT CATEGORIES
          • Logic Equivalence Checking
          • SoC Implementation and Floorplanning
          • Functional ECO
          • Low-Power Validation
          • Synthesis
          • Power Analysis
          • Constraints and CDC Signoff
          • Silicon Signoff and Verification
          • Library Characterization
          • Test
        • FEATURED PRODUCTS
          • Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
          • Voltus IC Power Integrity Solution
      • 客製IC/類比/RF設計
        • PRODUCT CATEGORIES
          • Circuit Design
          • Circuit Simulation
          • Layout Design
          • Layout Verification
          • Library Characterization
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • 系統設計與驗證
        • PRODUCT CATEGORIES
          • Debug Analysis
          • Virtual Prototyping
          • Emulation and Prototyping
          • Static and Formal Verification
          • Planning and Management
          • Simulation
          • Software-Driven Verification
          • Verification IP
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
      • IP
        • PRODUCT CATEGORIES
          • Denali Memory Interface and Storage IP
          • 112G/56G SerDes
          • PCIe and CXL
          • Tensilica Processor IP
          • Chiplet and D2D
          • Interface IP
        • RESOURCES
          • Discover PCIe
      • IC封裝設計與分析
        • PRODUCT CATEGORIES
          • Cross-Platform Co-Design and Analysis
          • IC Package Design
          • SI/PI Analysis
          • SI/PI Analysis Point Tools
          • Flows
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          • AWR Free Trial
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          • Augmented Reality Lab Tools
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  • 2018
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  • 1 May 2018

Cadence Supports New TSMC WoW Advanced Packaging Technology

Full suite of Cadence digital, signoff and custom/analog IC design tools coupled with advanced IC package design and analysis tools optimized for TSMC WoW technology

SAN JOSE, Calif., 01 May 2018

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its full suite of Cadence® digital, signoff and custom/analog IC design tools, along with advanced IC packaging design solutions, support the new TSMC Wafer-on-Wafer (WoW) stacking technology.

For more information on the Cadence solutions that support the TSMC WoW technology, visit www.cadence.com/go/wowcowosinfo.  

Support for WoW Advanced Packaging Technology

Cadence provides flows, tools and methodologies that enable TSMC customers to manage the top-level connectivity and verification of their chip integration solutions as part of the overall design process.

The Cadence tools have been optimized to provide a complete integrated flow for implementing WoW chip integration techniques within the existing toolchain and are as follows:

  • Innovus™ Implementation System: Supports single database top-die including front/back-side routing and backside-through-silicon-via (BTSV) support, creating connections between multiple dice
  • Quantus™ Extraction Solution: Supports back-side routing layers, sub-circuit replacement for BTSV and die-to-die interface coupling capacitance extraction, enabling electrical analysis between the dice
  • Voltus™ IC Power Integrity Solution: Provides die-level power map generation, enabling concurrent power analysis of multiple dice
  • Tempus™ Timing Signoff Solution: Provides multi-die static timing analysis (STA) support, enabling a checking of timing paths that cross multiple dice
  • Physical Verification System (PVS): Offers design rule checking (DRC) and layout vs. schematic (LVS) for die with BTSV, interface alignment and connectivity checks, ensuring that the two dice connect properly
  • Virtuoso® Platform: Includes features for bump placement and alignment on top of the existing PDK via the Virtuoso Incremental Technology Database (ITDB), creating connections between multiple dice
  • OrbitIO™ interconnect designer: Provides interface connectivity,  device flattening, port connectivity and configurable module definitions to manage top-level connectivity, enabling unified planning of die interconnect and alignment
  • Sigrity™ PowerSI® 3D-EM Extraction Option: Offers electrical modeling of the combined die and interposer, validating that the power and ground distribution is sufficient for multiple dice
  • Sigrity PowerDC™ technology: Thermal analysis solution with interposer and die analysis capabilities that allow co-simulation with Voltus IC Power Integrity Solution, enabling inclusion of temperature into concurrent electromigration analysis of multiple dice
  • Sigrity XcitePI™ Extraction:  Provides accurate interposer-level interconnect model extraction, enabling validation of high-speed signal propagation in the time and frequency domains
  • Sigrity SystemSI™ technology: Automatic construction of complete model-based interconnect topologies used to drive simultaneous switching noise (SSN/SSO) analysis for concise eye-diagram validation

“The new WoW reference flow complements our established InFO and CoWoS® chip integration solutions and gives customers more flexibility to use advanced packaging techniques,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “Cadence’s strong support for our packaging technologies is instrumental in enabling our mutual customers to achieve the benefits our solutions have to offer.”

“Cadence has a rich history in supporting TSMC’s solutions, and our support for TSMC’s WoW technology lets design engineers deploy the latest packaging techniques so they can get to market faster,” said Tom Beckley, senior vice president and general manager in the Custom IC & PCB Group at Cadence. “Our continued support for TSMC advanced packaging technologies also highlights our close working relationship with TSMC, and we are committed to ensuring customers have access to all the latest technologies to achieve their design goals.”

About Cadence

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence® software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company’s System Design Enablement strategy helps customers develop differentiated products—from chips to boards to systems—in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For. Learn more at www.cadence.com.

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