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    • DESIGN EXCELLENCE
      • 數位設計流程
        • Logic Equivalence Checking
        • Innovus Implementation and Floorplanning
        • Functional ECO
        • Low-Power Validation
        • Synthesis
        • Power Analysis
        • Constraints and CDC Signoff
        • Silicon Signoff and Verification
        • Library Characterization
        • Test
        • Flows
      • 客製IC/類比/RF設計
        • Circuit Design
        • Circuit Simulation
        • Layout Design
        • Layout Verification
        • Library Characterization
        • RF / Microwave Solutions
        • Flows
      • 系統設計與驗證
        • Debug Analysis
        • Emulation
        • Formal and Static Verification
        • FPGA-Based Prototyping
        • Planning and Management
        • Simulation
        • Software-Driven Verification
        • Verification IP
        • System-Level Verification IP
        • Flows
      • IP
        • Interface IP
        • Denali Memory IP
        • Tensilica Processor IP
        • Analog IP
        • System / Peripherals IP
        • Verification IP
      • IC封裝設計與分析
        • Cross-Platform Co-Design and Analysis
        • IC Package Design
        • SI/PI Analysis
        • SI/PI Analysis Point Tools
        • Flows
    • SYSTEM INNOVATION
      • 系統分析
        • Electromagnetic Solutions
        • RF / Microwave Design
        • Thermal Solutions
        • System Analysis Resources Hub
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      • PCB設計與分析
        • Design Authoring
        • PCB Layout
        • Library and Design Data Management
        • Analog/Mixed-Signal Simulation
        • SI/PI Analysis
        • SI/PI Analysis Point Tools
        • What's New in Allegro
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  • 27 Jan 2015

Cadence Expands Sigrity 2015 Technology Portfolio with New Products, a Key Feature Update and Flexible Licensing Options

SAN JOSE, Calif., 26 Jan 2015

HIGHLIGHTS:
  • New Sigrity Parallel Computing 4-pack enables efficient product creation with 3X speedup in signoff-accurate PCB extraction
  • Updated power-aware system signal integrity (SI) feature now supports LPDDR4 analysis with full JEDEC compliance checking
  • Flexible licensing options available for small analysis teams with big analysis requirements
Cadence Design Systems, Inc. (NASDAQ: CDNS), today announced an expanded Cadence® Sigrity™ technology portfolio with the Sigrity Parallel Computing 4-pack and the Sigrity System Explorer, an updated power-aware system signal integrity (SI) feature, as well as flexible purchasing options for PCB and IC Package design and analysis. The Sigrity technology portfolio enables product creation efficiency by increasing signoff-level PCB extraction accuracy.

To learn more about Sigrity solutions, visit: www.cadence.com/news/sigrity2015.

"The Sigrity 2015 portfolio release of implementation-linked analysis solutions targets critical design goals for higher-speed and lower-power electronic products, especially relevant for mobile and Internet of Things markets," said Vinod Kariat, vice president of R&D, Custom IC and PCB Group at Cadence. "Designers can utilize our new features to enable LPDDR4 sign-off along with simple yet cost-effective licensing for both distributed processing speed-up and multiple tool access by designers with a breadth of application needs."

New Products
  • Sigrity Parallel Computing 4-pack is a license that allows designers to run parallel computing tasks across four additional computers, thereby accelerating product creation time and tripling the speed of PCB extraction of signoff-accurate interconnect models.
  • Sigrity System Explorer features general purpose topology exploration, enabling power-aware signal integrity and transient power integrity (PI) analysis across multiple fabrics.
Updated Key Feature
  • The power-aware system signal integrity (SI) feature now supports LPDDR4 analysis with full JEDEC compliance checking, including bit error rate analysis with high capacity channel simulation for memory interface.
Licensing Options Cadence is also announcing several new product bundles, which provide flexible licensing options for small analysis teams with big analysis requirements. These bundles include:
  • Combined license for Allegro® Sigrity SI and Allegro Sigrity PI base products, when a single user is responsible for both SI and PI tasks.
  • Combined System SI license for both Serial Link and Parallel Bus analysis, when a single user is responsible for both memory interfaces and SerDes interfaces.
"Our collaboration with Cadence has allowed both engineering teams to develop tools that can improve our joint customers' product creation process. Working together, Cadence tools support the prototyping stage for our customers and provide a smooth transition to the test and measurement stage of product development," said Brian Reich, VP Performance Oscillocopes, Tektronix. "For example, in mobile memory, the Sigrity solution efficiently enables LPDDR4 designs through the prototype stage; while we provide our oscilloscope-based solution for electrical validation. Together, we help our joint customers accelerate their time-to-market."

About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.

For more information, please contact:
Cadence Newsroom
408-944-7039
newsroom@cadence.com


© 2015 Cadence Design Systems, Inc. All rights reserved worldwide. Allegro, Cadence and the Cadence logo are registered trademarks of, and Sigrity is a trademark of, Cadence Design Systems, Inc. in the United States and other countries.

Media Contacts

For more information, please contact:

Cadence Newsroom

408.944.7039

newsroom@cadence.com

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