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- 10 Jul 2013
Cadence Significantly Accelerates Chip Design With New Virtuoso for Electrically Aware Design
SAN JOSE, Calif., 09 Jul 2013
HIGHLIGHTS:
Using this innovative new technology, engineers can electrically analyze, simulate and verify interconnect decisions in real time, resulting in layout that is electrically correct-by-construction. This real-time visibility lets engineers reduce conservative design practices - or "over-design" - that can negatively impact a chip's performance and area.
Virtuoso Layout Suite EAD delivers:
For more information about the Virtuoso Layout Suite EAD, please click here.
- Cadence Virtuoso Electrically Aware Design (EAD) can save engineers days to weeks of design time by enabling real-time parasitic extraction during layout.
- New product and methodology reduces need for multiple design iterations and "over design," translating to better performance and less area.
Using this innovative new technology, engineers can electrically analyze, simulate and verify interconnect decisions in real time, resulting in layout that is electrically correct-by-construction. This real-time visibility lets engineers reduce conservative design practices - or "over-design" - that can negatively impact a chip's performance and area.
Virtuoso Layout Suite EAD delivers:
- The ability to capture currents and voltages from simulations run in the Virtuoso Analog Design Environment, and pass that electrical information forward into the layout environment
- Management capabilities that enable circuit designers to set electrical constraints (like matched capacitance and resistance) and allow layout designers to observe in real-time if these constraints are being met
- A built-in interconnect parasitic extraction engine that rapidly evaluates layout as it is created and provides an in-design electrical view for real-time analysis and optimization
- Electromigration (EM) analysis that alerts layout engineers to any EM issues that are being created as the layout is drawn
- Partial layout re-simulation that helps prevent errors from getting buried deep in a packed layout, thus minimizing re-spins and reducing the need to "over-design"
- A greater level of collaboration between circuit designers and layout designers to achieve electrically correct-by-construction layout, regardless of where the team members are located
For more information about the Virtuoso Layout Suite EAD, please click here.
About Cadence
Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry. More information about the company, its products, and services is available at www.cadence.com.
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