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  • Cadence推出全新Virtuoso平台,提供優化系統設計並支援5nm先進製程節點與模擬驅動佈局

Cadence推出全新Virtuoso平台,提供優化系統設計並支援5nm先進製程節點與模擬驅動佈局

Hsinchu, Taiwan, 11 Apr 2018

重點整理:

  • 先進佈局方法與模擬驅動佈局提升高達50%生產力
  • 減少超過三倍的FinFET佈局工作量
  • 改善Virtuoso ADE模擬生產量多達3倍
  • 利用先進統計演算法將設計變異分析時間縮短約20%
  • Virtuoso ADE Verifier符合業界標準提升驗證效率30%
  • 強化版Virtuoso系統設計平台支援多技術與多PDK

全球電子設計創新領導廠商益華電腦(Cadence Design Systems, Inc.)推出Cadence® Virtuoso®客製IC設計平台的技術提升與擴展,用以改善電子系統及IC設計產能。其範圍幾乎涵蓋所有Virtuoso產品,提供完善的環境和生態系統,協助系統工程師研發、設計實現並分析複雜晶片、封裝、電路板及系統。

有關新版Virtuoso平台的詳細資訊,請見: https://www.cadence.com/go/virtuoso-whats-new.html

增強版Virtuoso系統設計平台

2018年Virtuoso平台最重要的強化在於提升去年推出即獲肯定的Virtuoso系統設計平台。強化後的Virtuoso系統設計平台可供系統工程師無縫編輯並分析複雜度高的異構系統,並讓封裝、光電、類比IC和RF IC工程師在單一平台上作業,充分利用Virtuoso平台最受信賴的完整設計應用。

新版系統設計環境的重點技術是能夠跨多重流程設計套件及技術,同時進行編輯。此一平台亦提供與Cadence SIP Layout及Sigrity™分析技術組合的無縫互用,構成全面性的晶圓至電路板設計工具。

Virtuoso先進節點設計與佈局

Cadence全新的Virtuoso平採用創新先進節點方法,可加速從22nm至5nm流程技術中的設計。Cadence透過與領先晶圓廠、生態系統合作夥伴及顧客的合作,成功開發出以創新方法自動管理流程複雜性的先進技術,幫助工程師專注於其設計目的。在電路設計與分析中,特別針對FinFET設計的先進統計演算法能夠及早發現電路差異,利用先進統計演算法將設計變異分析時間縮短約20%。

在佈局設計中,獨特的多網格系統能夠統整最新7nm及5nm流程的複雜設計規則,同時幫助工程師增加對於佈局與規劃技術的利用,從而大幅提升佈局設計產能。利用這些針對先進方法改進的技術能夠在7nm的製造設計上節省多達三倍的佈局工作量。

Virtuoso先進設計方法與自動化

Cadence研發多項提升類比設計和分析的技術。藉由強化整合Cadence Spectre®電路模擬器,提高模擬生產量並利用先進分析減少設計重複,Virtuoso類比設計環境(ADE)的模擬生產量提升高達三倍。Virtuoso ADE Verifier 也加入獨特功能,集中跨領域電性規格,將符合標準(例如ISO 26262)的難度降低約30%。

透過獨特的設計中技術,Virtuoso佈局環境從電性感知佈局演進至業界首創電性和模擬驅動佈局的過程中能夠確保電路完整性及效能。這種新穎的模擬驅動佈局有效解決關鍵電路和先進節點設計上的許多電遷移(EM)和寄生問題。為提高佈局自動化,新的環境中以突破性技術處理階層式平面規劃,並採用全新的放置和布線自動化技術的規劃能力提高佈局設計產能和生產量,並縮短佈局周轉時間。

有鑑於當今晶片的複雜度日益增加,最大的挑戰之一就是設計團隊的佈局任務分工。增強版的Virtuoso平台擁有創新的同步即時團隊設計編輯能力,可供團隊分配佈局任務及性能條件假設探究,對於設計規則檢查(DRC)修正、晶片完成和人工佈線方面特別有幫助。

Cadence預計,如此具備電性驅動佈線和走線編輯、即時設計編輯和革命性設計規劃技術的創新佈局環境,可將產能改善多達50%。

Bosch公司EDA資深專案經理Göran Jerke表示:「Bosch在設計任務關鍵系統時最講求的就是高度可靠性。我們需要EDA工具讓為我們的工程團隊能夠有效地設計、分析並佈局出符合我們可靠度要求的電路,同時不影響設計人員的整體產能。我們與Cadence長期的合作先後開創了在電性感知以及電性驅動佈局設計上的關鍵創新。」

Cadence客製化IC及PCB事業群資深副總裁兼總經理Tom Beckley 說:「我們的目標是在跨晶片、封裝、模組和電路板設計的互用流程上提供最完整的解決方案,幫助我們的顧客設計並驗證包括類比、混合訊號、RF和光電產品在內的異構系統。以Virtuoso電性感知設計佈局套組的成功為基礎,新推出的Virtuoso平台提供開創性的分析能力,以及電性驅動佈局的能力,促進更加完善的設計實現。這也使得我們對於最先進流程技術的支援延伸到5nm節點。藉由與領先晶圓廠、生態系統合作夥伴和顧客的合作,我們得以大幅改善客製及類比設計方法。」

 

© 2018 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo and the other Cadence marks found at www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.


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