Designers and architects have numerous implementation options to consider when designing artificial intelligence (AI) and machine learning (ML) applications—including graphics processing units, specialized neural network processors, or fully customized hardware.
For ultra-low-power applications such as local inferencing on battery-powered edge devices, custom hardware tailored to a single task is often chosen to achieve maximum power efficiency. AI hardware designers start with an abstract TensorFlow or Caffe model, then need a path to implement it in efficient hardware. Often, this path leverages high-level synthesis (HLS) to create high-quality RTL as quickly as possible.
To learn more about designing to achieve maximum power efficiency, join Cadence Education Services and Solutions Architect, Dave Apte for our free, one-hour live webinar “AI Accelerator Design with Stratus™ HLS.”
- What is HLS?
- Why is HLS being used to design AI / ML hardware?
- How does Stratus HLS support AI design?
- Demonstration: Designing an inferencing engine
To register for the “AI Accelerator Design with Stratus HLS” webinar, use the REGISTER button and sign in with your email and Cadence password, then select “Request” to register for the session. Once registered, you’ll receive a confirmation email containing all log-in details.
- Registration closes Tuesday, September 24
- Please ensure that you have received the log-in link / details by this date
- Seating is limited for this webinar—if you register, please plan on attending
For questions and inquiries, or issues with registration, reach out to us:
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To view our complete training offerings, visit the Education Services website.