Join us at this Cadence® Technology on Tour event to learn about the latest innovations, including machine learning and physically aware RTL synthesis, in digital implementation and signoff. The event provides a unique opportunity to meet the experts, network with industry colleagues, and share experiences, ideas, and insights on how to achieve the best power, performance, and area (PPA) with a full-flow RTL2GDS solution from Cadence.
Welcome and Registration
True Integrated Digital Full Flow
The Cadence Digital Implementation Flow has been fully integrated for many years. Sharing common engines and a user interface across the whole digital flow enables an easy- to- use, convergent flow, resulting in the best power, performance, and turnaround time. During this session, we will show how the latest 19.1 release continues to drive integration and automation with new technology such as mixed placement, power integrity analysis and optimization, physically aware RTL synthesis, and machine learningbased implementation. Key members of the Cadence R&D team will attend to discuss the latest innovations. Join this session to learn how the integrated Cadence full digital flow implements the most challenging 7nm designs.
Innovation In DFT
Modus DFT software is a comprehensive design for test solution that includes SCAN, compression, ATPG, LBIST, PMBIST, and diagnostics. In this session, we will discuss the unique Modus physically-aware test leadership highlighting our 2D-Elastic (2DE) SCAN compression to reduce area and routing congestion, along with Modus unified compression for SCAN and LBIST, which achieves a 2X speedup for in-field test. You will also learn about the Modus Test Point Insertion advantage for achieving highest coverage with minimal patterns as well as the industry-leading Modus advantage for volume diagnostics.
Intelligent Formal Verification
Increasingly aggressive synthesis transforms push the limits of logic equivalency checking (LEC). Cadence Conformal® Smart LEC is a major leap in LEC productivity with next- generation engines to deliver the highest convergence up to 4X faster. Conformal ECO is the only automated RTL-to-layout functional ECO tool. Learn how designers are using it to contain tapeout schedule impact for late-arriving design features and bug fixes.
Innovation in Electrical Signoff
There several steps in the design process required to achieving the best PPA in silicon. One of the last steps is signoff, which can impact a successful, on-time tape out. In this session, you will learn about our innovative integrated solutions in timing and power signoff, and library characterization. We will discuss new technology based on machine learning, that will improve your timing and IR drop closure simultaneously. This will not only help you achieve your best PPA, but it will also have a positive impact on meeting time- to- market schedules.