Please join Cadence in celebrating 50 years of the International Test Conference in Washington, DC.
With test in the critical path to delivering products, DFT, ATPG, and diagnostics solution integrated with physical design and synthesis are more important than ever. Are you compromising test quality or spending silicon area to ensure you meet your schedule? Have you reviewed your legacy methodology and tool chain?
Modus DFT—the fastest path from P&R to silicon debug
The Cadence® Modus DFT Solution is natively integrated with physical design and synthesis—delivering superior test results and improving physical convergence. Whether it is enabling the next-generation startups delivering advanced-node networking systems or supporting innovators in automotive semiconductors, Cadence can help.
Meetings
Schedule a private meeting during the conference for more in-depth discussions about test challenges and solutions by emailing Rob Knoth at knoth@cadence.com or visit www.cadence.com/modus to learn more about the Cadence® test solution.
Conference Participation
Monday, Nov 11
Tutorial: "Improving Test Quality of Digital ICs"—Featuring Cadence Cell-Aware Test
Presenter: Erik Jan Marinissen (imec), Adit D.Singh (Auburn University)
Tuesday, Nov 12
12:40 – 13:00
Corporate Forum: "Physical Realities and Possibilities for Test"
Speaker: Rob Knoth (Cadence)
Tuesday, Nov 12
17:00 – 18:30
Industrial Practice Paper: Optimized Physical DFT Synthesis of Unified Compression and LBIST for Automotive Applications
Authors: Christos Papameletis (Cadence), Vivek Chickermane (Cadence), Brian Foutz (Cadence), Sarthak Singhal (Cadence), and Krishna Chakravadhanula (Cadence)
Tuesday, Nov 12
17:00 – 18:30
Industrial Practice Paper: Application of Cell-Aware Test on an Advanced 3nm Technology Library
Authors: Zhan Gao, Min-Chun Hu, Rogier Baert, Bilal Chehab, Joseph Swenton (Cadence), Santosh Malagi (Cadence), Jos Huisken (Eindhoven University of Technology), Kees Goossens (Eindhoven University of Technology), and Erik Jan Marinissen (iMEC)
Wednesday, Nov 13
08:30 – 10:00
Session w1 Paper #3: Delay Test
Chair: Krishna Chakravadhanula (Cadence)
Wednesday, Nov 13
11:30 – 13:30
Poster: "Machine Learning-Driven Throughput Optimization of Volume Diagnosis Methodology"
Authors: Robert Redburn (IBM), Sameer Chillarige (Cadence), Nicholai L'Esperance (IBM), Jeff Zimmerman (IBM), Adisun Wheelock (IBM), Anil Malik (Cadence), Martin Amodeo (Cadence), Atul Chhabra (Cadence), and Bharath Nandakumar (Cadence)
Wednesday, Nov 13
17:00 – 18:30
Paper: Improved Diagnosis Methodology for Multi-Defect Scenarios in High-Compression Scan-Based Designs
Authors: Bharath Nandakumar (Cadence), Sameer Chillarige (Cadence), Anil Malik (Cadence), Atul Chhabra (Cadence), Wilson Pradeep (TI), and Prakash Narayanan (TI)
Wednesday, Nov 13
17:00 – 18:30
Panel: 3D Chip Products Are Now Really Taking Off: Is the Test Community Ready for It?
Panelists: Vivek Chickermane (Cadence), Adam Cron (Synopsys), Sandeep K. Goel (TSMC), Marita Villareal (Technoprobe)
Thursday, Nov 14
8:30 – 10:00
Industrial Practice Papers: The Challenges of Implementing an MBIST Interface: A Practical Application
Authors: Teresa McLaurin (Arm) and Rob Knoth (Cadence)
