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Date EVENT NAME TECHNOLOGY Location Event Type
23 Jun 2020 - 02 Jul 2020

Webinar Series: Thinking Outside the Chip

Learn how to overcome challenges in designing RFIC, RF, and RF SiP modules through this three-day webinar series.

RF Microwave Design Online Cadence Event
08 Jul 2020

Webinar: Achieving Voltage Drop Requirements Using Integrated Optimization and Signoff

During this webinar we will discuss the latest techniques for IR drop optimization within the Innovus Implementation System, such as IR-aware placement, clock tree synthesis and power grid wire sizing, all based on the integrated Voltus voltage and power analysis and Tempus timing sign off engines. Attend this webinar to learn how to close IR drop constraints using an IR-aware implementation flow. Limited to Cadence customers with access to the digital implementation flow.

Innovus, Tempus Timing Signoff, Digital Implementation Online Cadence Event
08 Jul 2020

Webinar: Accelerate Design Productivity with Virtuoso ADE Explorer and Assembler

Join Cadence Training and Lead Application Engineer Bertram Winter and Application Engineer Ashika Ashok for our free, one-hour live webinar. Learn more about how to easily master Virtuoso ADE Explorer and Assembler and increase your design productivity at the same time.

Custom IC Design Online Cadence Event
09 Jul 2020

Webinar: Chip-Level Thermal Analysis Using Celsius Thermal Solver

Transient thermal analysis is a critical factor in understanding thermal behavior, and the impact of dynamic thermal management on the performance of a chip, even more so for applications like automotive, data center, mobile, healthcare, and high-performance computing

Celsius Online Cadence Event
09 Jul 2020

Webinar: Digital Implementation and Signoff – A Full Flow Overview

Bigger and more complex designs translate to more challenging PPA targets. To meet these challenges, the Cadence integrated digital full-flow offers innovations that work across individual tool boundaries through the integration of core engines and key technologies. Watch this webinar to learn how the Cadence digital full flow and its underlying products can help you beat your PPA goals ahead of schedule.

Digital Implementation Online Cadence Event
10 Jul 2020

Webinar (Taiwan): Verify Clock Gates with the JasperGold SEC App

The Cadence JasperGold Sequential Equivalene Checking (SEC) App is the industry's most widely supported independent sequential equivalence checking product--providing a complete solution without the need for testbench development. Learn more about the app by joining Cadence for this free, one-hour live webinar.

JasperGold Online Cadence Event
15 Jul 2020

Webinar: Addressing the Signoff Crisis with Tempus Power Integrity

Attend this webinar. Tempus Power Integrity introduces an integrated IR drop/STA solution combining the accuracy and speed of Tempus STA with Voltus IR drop analysis. Coupled with Innovus Implementation and Tempus-ECO Option’s powerful IR avoidance and fixing capabilities, Tempus Power Integrity enables engineering teams to signoff the highest performing designs with utmost confidence. Limited to Cadence customers with access to the digital implementation flow.

Innovus, Tempus Timing Signoff, Digital Implementation Online Cadence Event
16 Jul 2020 - 16 Sep 2020

Webinar Series: Finding Verification Pitfalls Before They Get You

What if you could reduce rework by stamping out the pitfalls much earlier in the design cycle, saving countless hours of design frustration when you are up against your release deadlines? Join our four-part webinar series to learn about advanced verification techniques that can be applied to RF and analog designs, as well as a methodology for tracking your progress to final specification coverage of your analog/mixed-signal designs.

Virtuoso, Custom IC Design Online Cadence Event
22 Jul 2020

Webinar: How to Leverage Cadence Online Support to Your Advantage

Attend this webinar to learn how to use Cadence Online Support (COS) to your advantage. Limited to Cadence customers with access to the digital implementation flow.

Cadence Online Support, Digital Implementation Online Cadence Event
29 Jul 2020

Webinar: Full Flow Power Analysis and Optimization

Attend this webinar. We will cover the Cadence solutions for power analysis and optimization starting with early system-level analysis, through RTL-level architecture/microarchitecture, low power implementation, and finally to silicon signoff. Limited to Cadence customers with access to the digital implementation flow.

Palladium, Genus, Innovus, Digital Implementation Online Cadence Event