19 October 2021
|Date||EVENT NAME||TECHNOLOGY||Location||Event Type|
|25 Oct 2021 - 29 Oct 2021||
Join Cadence at NAFEMS World Congress. The conference will provide a forum for presenting a unique combination in innovative techniques and best practice methods that cover every aspect of engineering modelling, analysis and simulation. Check Cadence presentations in the conference as well as visit our virtual booth.
|System Analysis||Online||Industry Conference|
|26 Oct 2021 - 08 Dec 2021||
Learn the basics of CFD in eight classes across eight weeks and gain hands-on experience using commercial, flow-simulation software! This is a free online course.
|26 Oct 2021||
Join Cadence at the 2021 TSMC OIP Ecosystem Forum to learn how Cadence and TSMC are partnering to enable new technologies in today's data-centric world.
|Mixed Signal, Custom IC Design, Design IP, Digital Implementation||Online|
|26 Oct 2021 - 27 Oct 2021||
Join Cadence at DVCon Europe, where Matt Graham will be discussing "Smarter Verification Management" on a 1-hour workshop and Kanwarpal Singh and Bijiendra Mittra, as they discuss "Accelerated Signoff with JasperGold RTL Designer Apps". The two-day virtual conference offers keynotes, panel sessions, insightful presentations and tutorials.
|26 Oct 2021||
Join Cadence at the world’s largest event for women in engineering and technology. Visit the Cadence virtual exhibit on October 26, from 11:00am – 3:00pm CT to learn more about our culture and career opportunities.
|27 Oct 2021 - 30 Oct 2021||
The Linley Conferences have been called the highest quality of their kind by previous attendees because they provide a unique opportunity to hear, question, and network with key providers of advanced technology products. Join Cadence this year and learn about our Tensilica offerings at our two presentations and breakout session!
|27 Oct 2021||
Learn how to increase quality of your SoC’s while meeting project schedule. As well as shorten long test cycles and reduce the possibility of system-level bugs at the end of the SoC development cycle.
|Palladium, Protium X1, Protium||Online||Cadence Event|
|27 Oct 2021||
Join this webinar to learn how Xcelium ML can be a game changer for your verification flow, providing up to 5X regression throughput saving significant time and compute resources.
|02 Nov 2021||
This webinar will demonstrate the ways in which the AWR Design Environment V16 platform supports an RF-to-PCB workflow using a new unified library import wizard to convert Allegro PCB Editor symbols, footprints, and PCB technology file into an AWR process design kit (PDK) that can be used to create an Allegro technology-compatible RF design using standard design entry and simulation methods. Upon completion of the design, the RF engineer can export the schematic and layout of the sub-circuit with all the underlying hierarchy into a design library for direct integration into Allegro schematic capture and layout tools.
|RF Microwave Design, Allegro, PCB Design||Online||Cadence Event|
|09 Nov 2021 - 10 Nov 2021||
Low power DRAM is being adopted in a wide array of markets, including automotive, PCs and networking systems built for 5G and AI applications. Join us to learn how to overcome the verification challenges from checking the specification compliancy of your IP design to integration and performance measurement when moving to your System-level.