- C++ Language Fundamentals for Design and Verification
- Essential SystemVerilog for UVM
- Extend the Language Using Specman e Macros!
- Foundations of Metric Driven Verification
- Incisive Functional Safety Simulator
- Incisive SystemC, VHDL, and Verilog Simulation
- JasperGold Formal Expert
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- Level Up Your RTL Bring-Up: Clean RTL Faster Without Simulation!
- Low-Power Simulation with CPF
- Low-Power Simulation with IEEE Std 1801 UPF
- Metric Driven Verification Using Cadence vManager
- Perl for EDA Engineering
- Perspec System Verifier – Basic
- Protium Rapid Prototyping Platform
- SVA, Formal and JasperGold® Fundamentals for Designers
- Specman Advanced Verification
- Specman Fundamentals for Block-Level Environment Developers
- SystemC Language Fundamentals
- SystemC Synthesis with Stratus HLS
- SystemC Transaction-Level Modeling (TLM 2.0)
- SystemVerilog Accelerated Verification with UVM
- SystemVerilog Advanced Register Verification Using UVM
- SystemVerilog Assertions
- SystemVerilog for Design and Verification
- Tcl Scripting for EDA + Intro to Tk
- VHDL Language and Application
- VIP Basic Building Blocks and Usage
- Verilog Language and Application
- Xcelium Integrated Coverage
- Xcelium Simulator
- vManager Tool Usage in Batch Mode
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System Design and Verification
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Genus Synthesis Solution v16.1
This online class features the Cadence® Genus™ Synthesis Solution with next generation synthesis capabilities and how SoC design productivity gap is filled by Genus