- Behavioral Modeling with Verilog-AMS
- C++ Language Fundamentals
- Essential SystemVerilog for UVM
- PCB Design at RF - Multi-Gigabit Transmission, EMI Control, and PCB Materials
- Perl for EDA Engineering
- Specman Advanced Verification
- Specman Fundamentals for Block-Level Environment Developers
- SystemC Language Fundamentals
- SystemC Synthesis with Stratus HLS
- SystemC Transaction-Level Modeling (TLM 2.0)
- SystemVerilog Accelerated Verification with UVM
- SystemVerilog Advanced Register Verification Using UVM
- SystemVerilog Assertions
- SystemVerilog for Design and Verification
- SystemVerilog for Verification
- Tcl Scripting for EDA + Intro to Tk
- VHDL Language and Application
- avatar Verilog Language and Application
Languages and Methodologies Learning Map
Cadence Training Services learning maps provide a comprehensive visual overview of the learning opportunities for Cadence customers. They provide recommended course flows as well as tool experience and knowledge levels to guide students through a complete learning plan. Learning Maps cover all Cadence Technologies and reference courses available worldwide.
语言和方法学学习计划
Cadence Training Services 学习计划以直观的方式向 Cadence 客户展示了所有学习机会。该学习计划提供推荐的课程系列以及工具经验和知识水平，引导学生完成整个学习计划。学习计划涵盖了全球所有可用的 Cadence 技术和参考课程。
Languages and Methodologies