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  • 产品

    • Products

      Cadence.AI

      • Millennium Platform

        AI-driven digital twin supercomputer

      • Cadence Cerebrus AI Studio

        Multi-block, multi-user SoC design platform

      • Optimality Intelligent System Explorer

        AI-driven Multiphysics analysis

      • Verisium Verification Platform

        AI-driven verification platform

      • Allegro X AI

        AI-driven PCB Design

      • Tensilica AI Platform

        On-device AI IP

    • Products

      IC 设计和验证

      • Virtuoso Studio

        Analog and custom IC design

      • Spectre 仿真

        Analog and mixed-signal SoC verification

      • Innovus+ Platform

        Synthesis and implementation for advanced nodes

      • Xcelium Logic Simulation

        IP and SoC design verification

      • Silicon Solutions

        Protocol IP and Compute IP, including Tensilica IP

      • Palladium 和 Protium

        Emulation and prototyping platforms

    • Products

      System Design & Analysis

      • Allegro X Design Platform

        System and PCB design platform

      • Allegro X Adv Package Designer Platform

        IC packaging design and analysis platform

      • Sigrity X Platform

        Signal and power integrity analysis platform

      • AWR Design Environment Platform

        RF and microwave development platform

      • Cadence Reality Digital Twin Platform

        Data center design and management platform

      • Fidelity CFD Platform

        Computational fluid dynamics platform

    • All Digital Design and Signoff Products
    • All PCB Design Products
    • All Verification Products
    • All Molecular Simulation Products
    • All Cadence Cloud Services and Solutions
    • All Products (A-Z)
    • All Analog IC Design Products
    • All 3D-IC Design Products
    • All 3D Electromagnetic Analysis Products
    • All Thermal Analysis Products
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    • 5G系统与子系统

    • 航空航天与防御

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    • 超大规模计算

    • 生命科学

    Services

    • Services Overview

    技术方案

    • Artificial Intelligence

    • 3D-IC设计

    • Advanced Node

    • Arm-Based Solutions

    • Cloud 解决方案

    • Computational Fluid Dynamics

    • Functional Safety

    • 低功耗设计

    • 混合信号设计

    • Molecular Simulation

    • Multiphysics System Analysis

    • Photonics

    • 射频/微波

    Designed with Cadence See how our customers create innovative products with Cadence
    Explore Cadence Cloud Now Explore Cadence Cloud Now
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    • 线上技术支持

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    • 技术论坛

    • OnCloud Help Center

    • Doc Assistant

    培训

    • Computational Fluid Dynamics

    • 定制IC/模拟/设计

    • Digital Design and Signoff

    • IC封装

    • 设计语言及方法学

    • Mixed-Signal Design Modeling, Simulation, and Verification

    • Onboarding Curricula

    • PCB设计

    • Reality DC

    • 系统设计与验证

    • Tech Domain Certification Programs

    • Tensilica处理器IP

    Link for support software downloads Stay up to date with the latest software
    Cadence award-winning online support available 24/7
    Connect with expert users in our Community Forums
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  • Schematic Capture for EEs Onboarding



Schematic Capture for EEs Onboarding Training

Instructor-Led Schedule
Online Courses
日期 版本 国家/地区 位置
Scheduled upon demandOn demand EXPRESS INTERESTINQUIRE
版本 区域
23.1 Online ENROLL
Other Versions Online EXPRESS INTERESTINQUIRE

Length: 6.6 Days (53 hours)

Course Description

This learning plan will provide in-depth knowledge of the Allegro X System Capture schematic entry tool, high-speed constraint management, and Sigrity Aurora. You will start with a brief introduction to the Pulse Data Platform, followed by modules using the Allegro X System Capture schematic entry tool. You will then explore the Allegro X PCB  Editor High-Speed Constraints, followed by the Sigrity Aurora tool.

Learning Objectives

After completing the courses, you will be able to:

  • Introduction to Pulse
Identify the key attributes of the Pulse Data Platform
  • Allegro X System Capture
Create a System Capture project
Create flat and hierarchical System Capture designs
Create DE-HDL library symbols in System Capture
Copy System Capture schematic pages
Import DE-HDL and System Capture blocks
Generate a BOM report
Edit properties and define routing rules
Export the design to PCB Editor for placement and routing
  • Allegro X High-Speed Constraint Management
Define specific net scheduling of high-speed nets
Match the propagation delay of nets and connections
Define minimum and maximum propagation delays for nets and connections
Identify high-speed constraint violations
Identify all the high-speed constraints that you can apply to the nets in your designs
Create spacing and physical constraints as well as area constraints and class-to-class rules
Customize worksheets
Create formula-based constraints
Create customized constraints using the SKILL programming language
Create return path constraints
  • Sigrity Aurora
Create, extract, and explore topologies
Run solution space analysis
Create an electrical constraint set
Apply constraints to drive placement and routing
Analyze nets on the routed board design for signal integrity
Use the Workflow Manager to analyze impedance, crosstalk and IR Drop on a PCB

Software Used in This Course

  • Please refer to the individual course datasheets for the software used.

Software Release(s)

Please refer to the individual course datasheets for the versions used.

Modules in this Course

The Onboarding class contains the following:
  • Introduction to Pulse
  • Allegro X System Capture
  • Allegro X High-Speed Constraint Management
  • Sigrity Aurora

Audience

  • CAD Engineers
  • Electrical Engineers
  • Layout Designers
  • PCB Designers
  • PCB Layout Designers

Prerequisites

  • You must have a working knowledge of the front-to-back PCB design flow

Related Courses

Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.


Course ID: 86367

CONTACT TRAINING

 
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Genus Synthesis Solution v16.1

This online class features the Cadence® Genus™ Synthesis Solution with next generation synthesis capabilities and how SoC design productivity gap is filled by Genus

COURSE DETAILS

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Mixed-Signal Simulation Using Spectre AMS Designer

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