Length : 1 day
Course Description
This course is based on the Stylus Common UI, which is a limited release in Innovus™ 19.1. Please consult with your Cadence AE before deciding to take this course instead of the course called Innovus Clock Concurrent Optimization Technology for Clock Tree Synthesis, which is based on the default UI and not on the Stylus UI.
In this course, you learn how to use the Clock Concurrent Optimization (CCOpt™) technology which is integrated into the Innovus Implementation System software to achieve the best clock tree for your power, performance and area (PPA) targets for your design. You learn clock tree theory and concepts as well as practical guides on how to set up properties as well as techniques to implement and debug the generated tree with the Clock Tree Debugger (CTD) tool.
Learning Objectives
After completing this course, you will be able to:
- Implement the clock tree using CCOpt technology using the generated constraints
- Specify clock properties to customize the clock tree including:
- Defining route types, CTS cells, stop and ignore pins
- Modifying source latency settings inhierarchical implementation to meet timing at the block level
- Analyze and debug the tree using the information in the log file
- Analyze the QoR of the generated tree
- Assess how CCOpt analyzes chains between register stages and:
- Recognize when CCOpt uses slack in chains to meet timing
- Review the log file and determine how the worst chain analysis report can provide additional information about why timing could not be met
- Run the Clock Tree Debugger in trial and cluster modes of CCOpt to determine causes for unmet clock targets
- Evaluate the advantages and disadvantages of various clock structures
- Implement a flexible H-tree
Software Used in This Course
- Innovus Implementation System
Software Release(s)
INNOVUS191
Modules in this Course
- Setting Up and Running CCOpt Clock Tree Synthesis
- CCOpt Debug, Analysis and Tuning
- Implementing H-Trees and Multi-Tap CTS
- Clock Tree Synthesis Overview
- Clock Constraints in SDC
Audience
- Physical Design Engineers
- Chip Designers
Prerequisites
You must have experience with or knowledge of the following:
- Innovus Implementation System software
Related Courses
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
Course ID: 86230
