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Genus Synthesis Solution
日期 | 版本 | 国家/地区 | 位置 | |
---|---|---|---|---|
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
版本 | 区域 | |
---|---|---|
19.1 | Online | ENROLL |
17.1M | Online | ENROLL |
17.1 | Online | ENROLL |
Other Versions | Online | EXPRESS INTERESTINQUIRE |
Length: 2 days (16 Hours)
Course Description
In this course, you learn about the features of the Cadence® Genus™ Synthesis Solution with next generation synthesis capabilities (massively parallel, tight correlation, RTL design focus and Architecture level PPA) and how SoC design productivity gap is filled by Genus. You learn several techniques to constraint designs, run static timing analysis, evaluate datapath logic, run physical synthesis, optimize for low-power structures, analyze DFT (design for testability) constraints, and interface with other tools. You will be able to identify the steps required to perform logic optimization for digital design and generate various input and output files. You also learn to run complete synthesis flow on a design with the given specifications and optimize it for area, timing and power.
Note: This course is based on the Legacy User Interface and not the Stylus Common User Interface.
Learning Objectives
After completing this course, you will be able to:
- Apply the recommended global synthesis flow using the Cadence Genus Synthesis Solution
- Navigate the design database and manipulate design objects
- Constraint designs for global synthesis and run static timing analysis
- Optimize RTL designs for timing and area using several strategies
- Diagnose and analyze synthesis results
- Use the extended datapath features
- Optimize designs using the physical synthesis flow
- Analyze and synthesize the design for low-power structures
- Constraint the design for testability (DFT)
- Identify the interface to Conformal® equivalence checker and other tools
Software Used in This Course
Genus Synthesis SolutionSoftware Release(s)
Genus 19.1
Modules in this Course
- Overview of Genus Synthesis Solution
- Genus Synthesis Solution Fundamentals
- Datapath Synthesis
- Debug Design Scenarios
- Genus Physical Synthesis
- Low-Power Optimization
- Test Synthesis
- Logic Equivalence Checking
- Interfacing with Other Tools
Audience
- ASIC Designers
- Digital IC Designers
- Logic Designers
Prerequisites
You must have experience with or knowledge of the following:
- Any HDL such as Verilog (recommended) or VHDL
- Synthesis and ASIC design flow basics
- Static Timing Analysis
Or you must have completed the following courses:
Related Courses
- Conformal Equivalence Checking
- Innovus Digital Implementation (Block)
- Innovus Digital Implementation (Hierarchical)
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
ONLINE TRAINING
Genus Synthesis Solution v16.1
This online class features the Cadence® Genus™ Synthesis Solution with next generation synthesis capabilities and how SoC design productivity gap is filled by Genus

"It was worth attending the training. The trainer was quite well aware of our questions and interests. He held the lecture vividly, which resulted in my good concentration despite the tough schedule."
C. Chen, Socionext

“Very beneficial”
Federico Quaglio, u-blox

"Very good. Liked the expertise of the presenter.”
Ludovic Rota, ON Semiconductor

"Well designed course!"
Umut Eksi, IMEC