Genus Synthesis Solution

Length : 2 days

Course Description

In this course, you learn about the features of the Cadence^® Genus^™ Synthesis Solution with next generation synthesis capabilities (massively parallel, tight correlation, RTL design focus and Architecture level PPA) and how SoC design productivity gap is filled by Genus. You learn several techniques to constrain designs, run static timing analysis, evaluate datapath logic, run physical synthesis, optimize for low-power structures, analyze DFT (design for testability) constraints, and interface with other tools. You will be able to identify the steps required to perform logic optimization for digital design and generate various input and output files. You also learn to run complete synthesis flow on a design with the given specifications and optimize it for area, timing, and power.

Note: This course is based on the Legacy User Interface and not the Stylus Common User Interface.

Learning Objectives

After completing this course, you will be able to:

• Apply the recommended global synthesis flow using the Cadence Genus Synthesis Solution
• Navigate the design database and manipulate design objects
• Constrain designs for global synthesis and run static timing analysis
• Optimize RTL designs for timing and area using several strategies
• Diagnose and analyze synthesis results
• Use the extended datapath features
• Optimize designs using the physical synthesis flow
• Analyze and synthesize the design for low-power structures
• Constrain the design for testability (DFT)
• Identify the interface to Conformal^® equivalence checker and other tools

Software Used in This Course

Genus Synthesis Solution

Software Release(s)

Genus 17.1

Modules in this Course

• Overview of Genus Synthesis Solution
• Genus Synthesis Solution Fundamentals
• Debug Design Scenarios
• Genus Physical Synthesis
• Low-Power Optimization
• Test Synthesis
• Logic Equivalence Checking
• Interfacing with Other Tools

Audience

• ASIC Designers
• Digital IC Designers
• Logic Designers

Prerequisites

You must have experience with or knowledge of the following:

• Any HDL such as Verilog (recommended) or VHDL
• Synthesis and ASIC design flow basics
• Static Timing Analysis

Or you must have completed the following courses:

• Basic Static Timing Analysis
• Verilog Language and Application