Quantus Transistor-Level T1: Overview and Technology Setup

Learning Objectives

After completing this course, you will be able to:

• Assess parasitic extraction challenges in design closure
• Elicit features of Quantus Extraction Solution
• Illustrate the Quantus licensing scheme
• Get an overview of Techgen–Quantus flow to create qrcTechFile
• Define the Pegasus-Quantus flow and the QCI flow
• Create the Techgen Input Files incorporating Manufacturing Effects
• Explore Techgen simulation and compilation steps
• Set up the Quantus Extraction Solution environment
• Compare Single vs. Multi-Corner extraction
• Set up and create Extracted View with control files
• Perform Quantus Extraction from the command line
• Use distributed processing (parallelism) to speed up extraction

Software Used in This Course

• Quantus Extraction Solution
• Pegasus^™ Verification System
• Virtuoso Layout Suite

Software Release(s)

EXT191, PEGASUS191, IC618

Modules in this Course

• Overview of Quantus Extraction
• Quantus Extraction Technology Setup

Audience

• Physical Verification and Extraction Designers who need to address parasitic issues in their design

Prerequisites

You must have:

• Knowledge and experience with physical design, verification and extraction
• Familiarity with the Virtuoso Layout Suite
• Familiarity with basic concepts of design parasitics, EMIR effects and simulation

Related Courses

• Quantus Transistor-Level T2: Parasitic Extraction
• Quantus Transistor-Level T3: Extracted View Flows and Advanced Features
• Virtuoso Layout Design Basics
• Physical Verification System
• Assura Parasitic Extraction (RCX)
• Cadence QRC Techgen Developer
• Virtuoso Analog Design Environment
• High-Performance Simulation Using Spectre Simulators

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