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Quantus Transistor-Level T1: Overview and Technology Setup
日期 | 版本 | 国家/地区 | 位置 | |
---|---|---|---|---|
26 Mar 2020 | 19.1 | 法国 | Velizy-Paris 法国 |
ENROLL |
25 Jun 2020 | 19.1 | 法国 | Velizy-Paris 法国 |
ENROLL |
Scheduled upon demandOn demand | EXPRESS INTERESTINQUIRE |
Length : 1/2 day
Digital Badge Available:
Course Description
Quantus Extraction Solution - RLCK Extraction You Trust
For classroom delivery, this course is taught as a half-day session (4 hours).
The course is designed to offer user-level experience on the next generation parasitic extraction solution from Cadence® – Quantus™ Extraction Solution. You will learn the parasitic extraction challenges in design closure and Quantus Extraction Solution to tackle it. You will also see how Quantus Extraction Solution fits into the design flow and how to set up the extraction environment. You will then analyze the Quantus technology directory structure, explore extraction features and check the modes – GUI and command line – of effectively extracting parasitic resistance, capacitance and inductance. In this course, you use the Virtuoso® Layout Suite. The Quantus Extraction Solution is integrated into the Virtuoso menu bar for easy access.
Learning Objectives
After completing this course, you will be able to:
- Assess parasitic extraction challenges in design closure
- Elicit features of Quantus Extraction Solution
- Illustrate the Quantus licensing scheme
- Get an overview of Techgen–Quantus flow to create qrcTechFile
- Define the Pegasus-Quantus flow and the QCI flow
- Create the Techgen Input Files incorporating Manufacturing Effects
- Explore Techgen simulation and compilation steps
- Set up the Quantus Extraction Solution environment
- Compare Single vs. Multi-Corner extraction
- Set up and create Extracted View with control files
- Perform Quantus Extraction from the command line
- Use distributed processing (parallelism) to speed up extraction
Software Used in This Course
- Quantus Extraction Solution
- Pegasus™ Verification System
- Virtuoso Layout Suite
Software Release(s)
EXT191, PEGASUS191, IC618
Modules in this Course
- Overview of Quantus Extraction
- Quantus Extraction Technology Setup
Audience
- Physical Verification and Extraction Designers who need to address parasitic issues in their design
Prerequisites
You must have:
- Knowledge and experience with physical design, verification and extraction
- Familiarity with the Virtuoso Layout Suite
- Familiarity with basic concepts of design parasitics, EMIR effects and simulation
Related Courses
- Quantus Transistor-Level T2: Parasitic Extraction
- Quantus Transistor-Level T3: Extracted View Flows and Advanced Features
- Virtuoso Layout Design Basics
- Physical Verification System
- Assura Parasitic Extraction (RCX)
- Cadence QRC Techgen Developer
- Virtuoso Analog Design Environment
- High-Performance Simulation Using Spectre Simulators
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
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