Length: 1 day (8 Hours)
This is an Engineer Explorer series course. The Engineer Explorer courses explore advanced topics.
Design Reuse is the creation of a logical block and physical layout representing a standalone portion of a design. The logical and physical data is placed in a library for others to reuse. Any EDA user who has time-to-market pressures will benefit from Design Reuse. Design Reuse adds scalability and modularity to your design process, saving time and reducing error by facilitating the reuse of known good IP.
After completing this course, you will be able to:
- Create a subdesign state file
- Create a layout module file
- Document and store the reuse design
- Use properties to control reuse packaging
- Work with hierarchical constraints
- Make changes to subdesigns while in reuse
- Customize packaging with Occurrence Edit
- Apply reuse methodology to existing (flat) designs
- Use macros and parameters
Software Used in This Course
- Allegro Design Authoring (PS2000) with High Speed Option (PA1410)
- Allegro PCB Designer (PA3100)
SPB 17.2-2016 Base release or greater
Modules in This Course
- Exploring a Design Reuse Example
- Creating a Reusable Block
- Reusing Blocks in Other Designs
- Managing Changes
- Advanced Topics
- Engineering Managers
- PCB Designers
- Design Engineers
You must have experience with or knowledge of the following:
- Allegro Design Entry HDL and PCB Editor tools. This course does not teach basic tool operations.
- Hierarchical design and the need to reuse logical blocks and associated part placement and signal routing.
Or you must have completed the following course: