Length : 2 days
Course Description
This advanced Engineer Explorer course is intended primarily for custom design and layout engineers who are experienced in Virtuoso® Layout XL/GXL, Virtuoso Space-Based Router (VSR) and who also have some familiarity with the Innovus™ and Tempus™ design flow.
The flow begins in the Virtuoso environment where you create and modify high level blocks with pins using Virtuoso Floorplanner. You continue by porting that data to the digital environment through the OA database. After implementing the digital block, and verifying timing, you bring the design back into the Virtuoso tool for assembly, routing and signoff.
You learn an in-depth approach to implementing an analog and digital mixed-signal design. You use Virtuoso Layout XL/GXL, Virtuoso Floorplanner, the Innovus software, NanoRoute™ and Virtuoso Space-Based Router (VSR) for primary and assembly routing. To be successful in learning how the two design environments work together through the OpenAccess (OA) gateway, a working knowledge of Virtuoso XL and Innovus flow is required.
Learning Objectives
After completing this course, you will be able to:
- Understand and implement the mixed-signal design flow
- Explore and implement the Analog-on-Top (AoT) flow
- Examine and implement the productivity features for
- Mixed-signal flow
- Place-and-route constraints
- Common Power Format (CPF)
- Top-level static timing analysis (STA)
- OpenAccess-based ECO
- Full Timing Model (FTM)
- Verification
- Use Virtuoso Layout XL/GXL and Innovus Digital Implementation software
- Implement routing techniques in the Innovus and Virtuoso platforms
- Pass data between the Innovus and Virtuoso platforms
Software Used in This Course
- Virtuoso Layout Suites XL/GXL, Innovus, Tempus, EXT
Software Release(s)
- IC617.x, Innovus 15.x, Tempus 15.1
Course Agenda
Day 1
- Module 1:About This Course
- Module 2: Mixed-Signal Introduction to Analog-on-Top Design
- Module 3: OpenAccess Data Preparation
- Module 4: Virtuoso Mixed-Signal Floorplanning and Basic Design Guidelines
Day 2
- Module 5: Design Interoperability and Innovus Digital Flow Implementation
- Module 6: Top Level Chip Assembly
- Module 7: Top Level Constraints and Interconnect Routing
- Module 8: Full Timing Model and Top-Level Static Timing Analysis
Audience
- Digital and Analog Design Engineers
- Digital and Analog Layout Engineers
- CAD Department Engineers
- Project Leaders with Technical Background
Prerequisites
You must have experience with or knowledge of the following:
- Digital design
- Analog design
- Virtuoso Layout Suites XL/GXL
- Innovus
- Tempus
Or you must have completed the following courses:
Related Courses
Click here to view course learning maps, and here for complete course catalogs.
Course ID: 85035
