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In this course, which has been designed for user-level physical design verification, you run DRC, ERC, PERC, FastXOR and LVS checks to find and debug errors that are located during the checks. You set up options, run DRC, and use the debugger to locate and fix design rule violations. You set up and run ERC, use the debugger, and run the interactive short locator to find and fix errors. You set up options, run LVS, and use the LVS debug environment to locate and repair errors. You also explore the documentation system and Cadence® online support.
In this course, the Virtuoso® Layout Suite is used. The Physical Verification System (PVS) is integrated into the Virtuoso menus for easy access. You set up and run IPVS for post-edit DRC checking, and use FastXOR to compare a stream file with an existing OpenAccess cellview.
The final module of the course has a free-form lab exercise, which is to be done using the skills that you learned in the previous modules. You have a physical layout with multiple errors and you have minimal instructions. You find and fix the errors, so you have clean DRC, ERC, and LVS runs.
After completing this course, you will be able to:
- Use the Physical Verification System (PVS) to check your designs for design rule violations, for electrical rule violations, and to compare the schematic and layout designs for accuracy
- Set up and run DRC, ERC, IPVS, and LVS
- Use the debug environment to find and fix errors
- Select specific rule files for your checks
- Use the debug environment and interactive short Locator to find and fix power and ground shorts on large circuits
Software Used in This Course
- Virtuoso Layout Suite
- Physical Verification System
- Encounter Digital Implementation System
IC 188.8.131.520.8, PVS 15.1
Modules in this Course
- Set up, run, and debug
- IPVS Interactive in-design verification
- Running FastXOR
- Unscripted debugging of a multiple error circuit
- Physical layout designers who need to verify layout designs
You must have:
- Knowledge and experience with physical design and verification
- Familiarity with the Virtuoso Layout Suite
This course does not teach design or verification principles.
- Virtuoso Schematic Editor
- Virtuoso Layout Design Basics
- Virtuoso Connectivity-Driven Layout Transition
- Using Virtuoso Constraints Effectively
- Physical Verification Language Rules Writer