Length : 3 day(s)
Digital Badge Available:
Course Description
In this course, you use the Virtuoso® ADE Explorer and Spectre® Circuit Simulator to simulate analog circuits with Verilog-A models. Verilog-A is a high-level language that uses modules to describe the structure and behavior of analog systems and their components. You use the Verilog-A syntax, structure Verilog-A modules, and generate symbols for your Verilog-A cells for use in a system hierarchy. You also learn to format output data and to use waveform filters to improve simulation performance. Finally, you examine the AHDL Linter feature to detect potential bugs in the Verilog-A codes.
Learning Objectives
After completing this course, you will be able to:
- Determine the importance of the top-down design methodology for accelerating complex system development
- Write behavioral models of electrical circuits using the correct Verilog-A language and syntax
- Create, edit, and simulate a variety of analog models written in the Verilog-A language using the Virtuoso ADE Explorer and the command-line environment
- Verify that Verilog-A modules properly describe the intended function
- Use software design tools to facilitate model development
Software Used in This Course
- Cadence® Design Framework II
- Virtuoso Schematic Editor L, XL
- Virtuoso ADE Explorer
- Spectre Classic Simulator
- Virtuoso Visualization and Analysis XL
Software Release(s)
IC 6.1.7(ISR19), SPECTRE 17.1 (ISR4)
Modules in this Course
- Basic Modeling Concepts
- Verilog-A Flow and Simulation
- The Design of Verilog-A Modules
- Verilog-A Modeling Descriptions
- Analog Event Detection
- Analog Operators and Filters
- Verilog-A Functions and Operators
- Looping and Conditional Constructs
- User-Defined and System Functions
- Displaying and Printing Results
- AHDL Linter Checks
Audience
- Analog/Mixed-Signal Designers
- IC Designers
- Library Developers
- System-level IC Designers
Prerequisites
You must have experience with or knowledge of the following:
- Some programming, UNIX or Linux, a text editor
And experience with the following software:
- Virtuoso ADE Explorer
- Spectre Circuit Simulator
- Virtuoso Visualization and Analysis XL
Related Courses
Please see course learning maps at this link for a visual representation of courses and course relationships. Regional course catalogs may be viewed here.
SELF PACED ONLINE TRAINING
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Multiple online courses of one or more technology groups, for 12 months unlimited, per student
ONLINE TRAINING
Genus Synthesis Solution v16.1
This online class features the Cadence® Genus™ Synthesis Solution with next generation synthesis capabilities and how SoC design productivity gap is filled by Genus
The possibilities of Verilog-A are really impressive, and I was not aware of them, even using spectre for several years.”
Michael Langenbuch, Intel
“I was very impressed by the professional attitude of the lector and satisfied with the course information I received."
Jiri Lehocky, ONSemiconductor
"Very, very good. I like the compact way the topics are presented."
Michael Asam, Infineon Technologies
"The course was very beneficial for me. I like the teacher presenting very clearly."
Pavel Londak, ONSemiconductor
"The course was at my level. I liked that it was practical with exercises to test out what we learned."
Derek Bernardon, Infineon Technologies
"After this course I know how to improve my existent modules and (…) have several new concepts to implement using Verilog-A for memory compilers design needs and more. Verilog-A together with this course definitely opens the innovation box."
Dr. Andrey Karavaev, X-FAB
"I especially liked the complete documentation and lab descriptions. Cadence trainings are always very professional and a good learning opportunity."
Rosario Chiodo, Infineon
"I enjoyed learning this course. It is clear, well explained(...)and the labs are really good." -Online Course-
Bertrand Coulon, Melexis