China Public Training Classes Schedule (2018/Q4)
All Courses Learning Map
Cadence Training Services learning maps provide a comprehensive visual overview of the learning opportunities for Cadence customers. They provide recommended course flows as well as tool experience and knowledge levels to guide students through a complete learning plan. Learning Maps cover all Cadence Technologies and reference courses available worldwide.
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Custom IC / Analog / Microwave & RF Design
- 3D EM Analysis with Clarity in Microwave Office
- 5G mmWave Handset System Design – S1: Simulation and Verification of the RFIC (Transceiver)
- Advanced SKILL Language Programming
- Analog Circuit Design and Simulation Onboarding
- Analog Circuit Design and Simulation Onboarding
- Analog IC Design Implementation and Verification Academic Curriculum
- Analog Modeling and Simulation with SPICE
- Analyzing Simulation Results Using Virtuoso Visualization and Analysis
- Auto Place and Route (APR) for Virtuoso Studio – Device Level
- Cadence Analog IC Design Flow
- Design Checks and Asserts in Spectre Simulator
- Electromagnetic Simulations Using the EMX Solver
- FastSpice Simulations Using Spectre FX Simulator
- High-Performance Spectre Simulation
- Managing Analog Verification using ADE Verifier
- Microwave Office for RF Designers
- Pegasus Verification System
- Physical Verification Language Rules Writer
- Physical Verification System
- Planar EM Analysis in AWR Microwave Office
- Quantus Transistor-Level T1: Overview and Technology Setup
- Quantus Transistor-Level T2: Parasitic Extraction
- Quantus Transistor-Level T3: Extracted View Flows and Advanced Features
- Reliability Analysis in Virtuoso Studio
- SKILL Development of Parameterized Cells
- SKILL Language Programming
- SKILL Language Programming Fundamentals
- SKILL Language Programming Introduction
- Spectre FMC in Virtuoso ADE
- Spectre RF Analyses S1: Large-Signal Analyses Using Harmonic Balance and Shooting Newton
- Spectre RF Analysis Using Shooting Newton Method
- Spectre RF Analysis using Harmonic Balance
- Spectre Simulator Fundamentals S1: Spectre Basics
- Spectre Simulator Fundamentals S2: Large-Signal Analyses
- Spectre Simulator Fundamentals S3: Small-Signal Analyses
- Spectre Simulator Fundamentals S4: Measurement Description Language
- Transistor-Level Power Signoff with Voltus-XFi
- Using Spectre Effectively S1: Accelerating DC Analysis
- Using Spectre Effectively S2: Accelerating Transient Analysis
- Virtuoso ADE Explorer and Assembler S1: ADE Explorer and Single Test Corner Analysis
- Virtuoso ADE Explorer and Assembler S2: ADE Assembler and Multi Test Corner Analysis
- Virtuoso ADE Explorer and Assembler S3: Sweeping Variables and Simulating Corners
- Virtuoso ADE Explorer and Assembler S4: Monte Carlo Analysis, Real-Time Tuning and Run Plans
- Virtuoso ADE Verifier S1: Setup, Run and View Verification Results
- Virtuoso ADE Verifier S2: Reference Flow and Analog Coverage Using the Setup Library Assistant
- Virtuoso Abstract Generator
- Virtuoso Connectivity-Driven Layout Transition
- Virtuoso Floorplanner
- Virtuoso Heterogeneous Integration: EM Analysis of ICs Using the EMX Solver
- Virtuoso Layout Design Basics
- Virtuoso Layout Design Basics
- Virtuoso Layout Onboarding
- Virtuoso Layout Pro: T1 Environment and Basic Commands
- Virtuoso Layout Pro: T2 Create and Edit Commands
- Virtuoso Layout Pro: T3 Basic Commands
- Virtuoso Layout Pro: T4 Advanced Commands
- Virtuoso Layout Pro: T4 Advanced Commands
- Virtuoso Layout Pro: T5 Interactive Routing
- Virtuoso Layout Pro: T6 Constraint-Driven Flow and Power Routing
- Virtuoso Layout Pro: T7 Module Generator and Floorplanner
- Virtuoso Layout Pro: T8 Virtuoso Concurrent Layout Editing
- Virtuoso Layout Pro: T9 Virtuoso Design Planner
- Virtuoso Layout for Advanced Nodes
- Virtuoso Layout for Advanced Nodes: T1 Place and Route
- Virtuoso Layout for Advanced Nodes: T2 Electromigration
- Virtuoso Layout for Photonics Design - T1
- Virtuoso Schematic Editor
- Virtuoso Spectre Transient Noise
- Virtuoso Studio Features
- Virtuoso System Design Platform
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Digital Design and Signoff
- ATPG Flow with Modus DFT Software Solution
- Advanced Synthesis with Genus Stylus Common UI
- Artificial Intelligence and Machine Learning Fundamentals
- Basic Static Timing Analysis
- Cadence Cerebrus Intelligent Chip Explorer
- Cadence RTL-to-GDSII Flow
- Certus Signoff Closure Solution with Stylus Common UI
- Conformal ECO
- Conformal Equivalence Checking
- Conformal Low Power Verification Using IEEE 1801
- Conformal Low Power Verification with CPF
- Design for Test Fundamentals
- Digital Design and Signoff Academic Curriculum
- Digital IC Design Fundamentals
- Digital Physical Design Domain Certification
- Functional Safety Implementation and Verification with Midas
- Fundamentals of IEEE 1801 Low-Power Specification Format
- Genus Low-Power Synthesis Flow with IEEE 1801
- Genus Physical Synthesis Flow
- Genus Synthesis Solution with Stylus Common UI
- Innovus Block Implementation with Stylus Common UI
- Innovus Clock Concurrent Optimization Technology for Clock Tree Synthesis
- Innovus Clock Concurrent Optimization Technology with Stylus Common UI
- Innovus Hierarchical Implementation with Stylus Common UI
- Innovus Implementation System (Block)
- Innovus Implementation System (Hierarchical)
- Innovus Low-Power Flow with Stylus Common UI
- Introduction to Electronic Design Automation
- Joules Power Calculator
- Low-Power Flow with Innovus Implementation System
- Low-Power Synthesis Flow with Genus Stylus Common UI
- Midas Safety Platform Introduction
- Semiconductor 101
- Signoff Timing and Power Analysis Domain Certification
- Synthesis and Static Timing Analysis Domain Certification
- System Design and Verification, Digital Physical Design and Signoff Onboarding
- Tempus Signoff Timing Analysis and Closure
- Tempus Signoff Timing Analysis and Closure with Stylus Common UI
- Test Synthesis with Genus Stylus Common UI
- Virtuoso Digital Implementation
- Voltus Power Grid Analysis and Signoff with Stylus Common UI
- Voltus Power-Grid Analysis and Signoff
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IC Package
- Allegro Sigrity PI
- Allegro Sigrity Package Assessment and Model Extraction
- Allegro Sigrity SI Foundations
- Allegro X Advanced Package Designer
- Designing with Integrity 3D-IC
- OrbitIO System Planner
- Sigrity Aurora
- Sigrity PowerDC and OptimizePI
- Sigrity PowerDC and OptimizePI (Français)
- Sigrity SystemSI for Parallel Bus and Serial Link Analysis
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Languages and Methodologies
- Behavioral Modeling with Verilog-AMS
- C++ Language Fundamentals
- Essential SystemVerilog for UVM
- PCB Design at RF - Multi-Gigabit Transmission, EMI Control, and PCB Materials
- Perl for EDA Engineering
- Specman Advanced Verification
- Specman Fundamentals for Block-Level Environment Developers
- SystemC Language Fundamentals
- SystemC Synthesis with Stratus HLS
- SystemC Transaction-Level Modeling (TLM 2.0)
- SystemVerilog Accelerated Verification with UVM
- SystemVerilog Advanced Register Verification Using UVM
- SystemVerilog Assertions
- SystemVerilog for Design and Verification
- SystemVerilog for Verification
- Tcl Scripting for EDA + Intro to Tk
- VHDL Language and Application
- Verilog Language and Application
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Mixed-Signal Design Modeling, Simulation and Verification
- Analog Modeling with Verilog-A
- Analog-Mixed Signal Design Modeling Onboarding
- Analog-Mixed Signal Design Modeling Onboarding
- Behavioral Modeling with Verilog-AMS
- Command-Line Based Mixed-Signal Simulations with the Xcelium Use Model
- Mixed Signal Simulations Using Spectre AMS Designer
- Mixed Signal Verification with UVM
- Real Number Modeling with SystemVerilog
- Real Number Modeling with Verilog-AMS
- SimVision for Debugging Mixed-Signal Simulations
- SystemVerilog Real Number Modeling (SV-RNM) Based Advanced Verification
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Onboarding Curricula
- Analog Circuit Design and Simulation Onboarding
- Analog-Mixed Signal Design Modeling Onboarding
- EE/PCB Layout Designers Onboarding
- PCB Layout Designer Onboarding
- SI/PI Engineer Onboarding
- Schematic Capture for EEs Onboarding
- System Design and Verification, Digital Physical Design and Signoff Onboarding
- Virtuoso Layout Onboarding
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PCB Design
- Advanced Design Verification with the RAVEL Programming Language
- Advanced PSpice for Power Users
- Allegro DesignTrue DFM
- Allegro Sigrity PI
- Allegro Sigrity SI Foundations
- Allegro X Design Entry HDL Basics
- Allegro X Design Entry HDL Front-to-Back Flow
- Allegro X Design Entry HDL SKILL Programming Language
- Allegro X EDM Design Entry HDL Front-to-Back Flow
- Allegro X EDM PCB Librarian
- Allegro X High-Speed Constraint Management
- Allegro X PCB Editor Advanced Methodologies
- Allegro X PCB Editor Basic Techniques
- Allegro X PCB Editor Intermediate Techniques
- Allegro X PCB Editor SKILL Programming Language
- Allegro X PCB Router Basics
- Allegro X RF PCB
- Allegro X System Capture Basics
- Allegro X System Capture Front-to-Back Flow
- Allegro X Update Training
- Analog Simulation with PSpice
- Analog Simulation with PSpice using Design Entry HDL
- Analog Simulation with PSpice using System Capture
- Celsius Thermal Solver
- Clarity 3D Solver
- Clarity 3D Solver
- DC and Thermal Analysis with Celsius PowerDC
- DE-HDL Library Development using Allegro X System Capture
- DE-HDL Library Development using DE-HDL
- EE/PCB Layout Designers Onboarding
- Essential High-Speed PCB Design for Signal Integrity
- Model Generation and Analysis using PowerSI and Broadband SPICE
- Model Generation and Analysis using PowerSI and Broadband SPICE
- OrCAD X CIS
- OrCAD X Capture
- OrCAD X Capture Constraint Manager PCB Flow Basics
- OrCAD X Presto Basic Techniques
- PCB Design at RF - Multi-Gigabit Transmission, EMI Control, and PCB Materials
- PCB Layout Designer Onboarding
- PDN and Voltage Ripple Analysis with Sigrity X OptimizePI and SystemPI
- Printed Circuit Board (PCB) Design Fundamentals Academic Curriculum
- SI/PI Engineer Onboarding
- Schematic Capture for EEs Onboarding
- Sigrity Aurora
- Sigrity PowerDC and OptimizePI
- Sigrity PowerDC and OptimizePI (Français)
- Sigrity SystemSI for Parallel Bus and Serial Link Analysis
- SystemSI for Parallel Bus and Serial Link Analysis
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System Design and Verification
- C++ Language Fundamentals
- Digital Design and Verification Academic Curriculum
- Digital IC Design Fundamentals
- Essential SystemVerilog for UVM
- Foundations of Metric Driven Verification
- Front End Digital Design and Verification Language and Methodology Domain Certification
- Incisive Functional Safety Simulator
- Introduction to Tk
- Jasper App For Early Design Verification
- Jasper Design Bringup Training
- Jasper Formal Expert
- Jasper Formal Fundamentals
- Low-Power Simulation with CPF
- Low-Power Simulation with IEEE Std 1801 UPF
- MIDAS Safety Analysis Authoring
- MIDAS Verisium Manager Safety Flow
- Midas Safety Platform Introduction
- Palladium Introduction
- Perl for EDA Engineering
- Perspec System Verifier - Basic
- Perspec System Verifier - Basic
- Protium Introduction
- Simulation, Coverage, Debug, and Verification Planning & Management Domain Certification
- Specman Advanced Verification
- Specman Fundamentals for Block-Level Environment Developers
- System Design and Verification, Digital Physical Design and Signoff Onboarding
- System Verilog Assertions (SVA) and Formal Verification Domain Certification
- SystemC Language Fundamentals
- SystemC Synthesis with Stratus HLS
- SystemC Transaction-Level Modeling (TLM 2.0)
- SystemVerilog Accelerated Verification with UVM
- SystemVerilog Advanced Register Verification Using UVM
- SystemVerilog Assertions
- SystemVerilog for Design and Verification
- Tcl Scripting for EDA
- Tcl Scripting for EDA + Intro to Tk
- UCIe VIP Introduction
- VHDL Language and Application
- VIP Basic Building Blocks and Usage
- Verisium Debug
- Verisium Manager
- Xcelium Fault Simulator
- Xcelium Integrated Coverage
- Xcelium Simulator
- vManager Tool Usage in Batch Mode
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Tensilica Processor IP
- Tensilica Audio Codec API
- Tensilica ConnX B10 DSP
- Tensilica ConnX BBE32EP Baseband Engine
- Tensilica ConnX DSP Family
- Tensilica FloatingPoint DSP Family
- Tensilica Fusion F1 DSP
- Tensilica Fusion G3 DSP
- Tensilica HiFi 3 Audio Engine ISA
- Tensilica HiFi 4 DSP
- Tensilica HiFi 5 DSP
- Tensilica Instruction Extension Language and Design
- Tensilica MathX DSP Family
- Tensilica System Modeling using XTSC
- Tensilica Vision DSP Family
- Tensilica Xtensa Audio Framework
- Tensilica Xtensa LX Hardware Verification and EDA
- Tensilica Xtensa LX Processor Fundamentals
- Tensilica Xtensa LX Processor Interfaces
- Tensilica Xtensa NX Hardware Verification and EDA
- Tensilica Xtensa NX Processor Fundamentals
- Tensilica Xtensa NX Processor Interfaces
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Tech Domain Certification Programs
- Analog Design Analysis and Simulation Domain Certification
- Analog Physical Design and Verification Domain Certification
- Analog/Mixed Signal Circuit Modeling Domain Certification
- Digital Physical Design Domain Certification
- Front End Digital Design and Verification Language and Methodology Domain Certification
- Signoff Timing and Power Analysis Domain Certification
- Simulation, Coverage, Debug, and Verification Planning & Management Domain Certification
- Synthesis and Static Timing Analysis Domain Certification
- System Level Signal and Power Integrity Domain Certification
- System Verilog Assertions (SVA) and Formal Verification Domain Certification
ONLINE TRAINING
Genus Synthesis Solution v16.1
This online class features the Cadence® Genus™ Synthesis Solution with next generation synthesis capabilities and how SoC design productivity gap is filled by Genus