- 5G mmWave Handset System Design – S1: RFIC (Transceiver) Design
- Advanced SKILL Language Programming
- Analog Modeling and Simulation with SPICE
- Analog Modeling with Verilog-A
- Behavioral Modeling with VHDL-AMS
- Behavioral Modeling with Verilog-AMS
- Command-Line Based Mixed-Signal Simulations with the Xcelium Use Model
- Design Checks and Asserts
- High-Performance Spectre Simulation
- Mixed Signal Simulations Using Spectre AMS Designer
- Mixed Signal Simulations Using Spectre AMS Designer
- Pegasus Verification System
- Pegasus Verification System
- Physical Verification Language Rules Writer
- Physical Verification System
- Physical Verification System
- Quantus Transistor-Level T1: Overview and Technology Setup
- Quantus Transistor-Level T1: Overview and Technology Setup
- Quantus Transistor-Level T2: Parasitic Extraction
- Quantus Transistor-Level T2: Parasitic Extraction
- Quantus Transistor-Level T3: Extracted View Flows and Advanced Features
- Quantus Transistor-Level T3: Extracted View Flows and Advanced Features
- Real Modeling with SystemVerilog
- Real Modeling with SystemVerilog
- Real Modeling with Verilog-AMS
- SKILL Development of Parameterized Cells
- SKILL Language Programming
- SKILL Language Programming Fundamentals
- SKILL Language Programming Introduction
- SKILL Language Programming Introduction
- Simulation and Analysis Using OCEAN
- Simulation and Analysis Using OCEAN
- Spectre Accelerated Parallel Simulator
- Spectre Accelerated Parallel Simulator
- Spectre RF Analysis using Harmonic Balance
- Spectre RF Analysis using Shooting Newton Method
- Spectre Simulator Fundamentals S1: Spectre Basics
- Spectre Simulator Fundamentals S2: Large-Signal Analyses
- Spectre Simulator Fundamentals S3: Small-Signal Analyses
- Spectre Simulator Fundamentals S3: Small-Signal Analyses
- Spectre Simulator Fundamentals S4: Measurement Description Language
- Spectre Simulator Fundamentals S4: Measurement Description Language
- Spectre eXtensive Partitioning Simulator for Mixed-Signal Designs
- SystemVerilog Real Number Modeling (SV-RNM) Based Advanced Verification
- Variation Analysis Using the Virtuoso Variation Option
- Virtuoso ADE Explorer and Assembler S1: ADE Explorer and Single Test Corner Analysis
- Virtuoso ADE Explorer and Assembler S2: ADE Assembler and Multi Test Corner Analysis
- Virtuoso ADE Explorer and Assembler S3: Sweeping Variables and Simulating Corners
- Virtuoso ADE Explorer and Assembler S4: Monte Carlo Analysis, Real-Time Tuning and Run Plans
- Virtuoso ADE Verifier S1: Setup, Run and View Verification Results
- Virtuoso ADE Verifier S2: Reference Flow and Analog Coverage Using the Setup Library Assistant
- Virtuoso Abstract Generator
- Virtuoso Analog Design Environment
- Virtuoso Analog Simulation: T1 The Virtuoso Analog Design XL Environment
- Virtuoso Analog Simulation: T2 Creating Sweeps and Running Corner Analysis
- Virtuoso Analog Simulation: T3 Monte Carlo Simulations Using ADEXL
- Virtuoso Analog Simulation: T4 Sensitivity Analysis and Circuit Optimization Using ADE(G)XL
- Virtuoso Connectivity-Driven Layout Transition
- Virtuoso Floorplanner
- Virtuoso Layout Design Basics
- Virtuoso Layout Pro: T1 Environment and Basic Commands (L)
- Virtuoso Layout Pro: T2 Create and Edit Commands (L)
- Virtuoso Layout Pro: T3 Basic Commands (XL)
- Virtuoso Layout Pro: T4 Advanced Commands (XL)
- Virtuoso Layout Pro: T5 Interactive Routing (XL)
- Virtuoso Layout Pro: T6 Constraint-Driven Flow and Power Routing
- Virtuoso Layout Pro: T7 Module Generator and Floorplanner (XL/GXL)
- Virtuoso Layout Pro: T9 Virtuoso Design Planner
- Virtuoso Layout for Advanced Nodes
- Virtuoso Layout for Advanced Nodes and Methodology Platform
- Virtuoso Layout for Advanced Nodes and Methodology Platform
- Virtuoso Layout for Advanced Nodes: T1 Place and Route
- Virtuoso Layout for Advanced Nodes: T2 Electromigration
- Virtuoso Schematic Editor
- Virtuoso Simulation Driven Routing (SDR)
- Virtuoso Spectre Pro S1: DC Algorithm
- Virtuoso Spectre Pro S2: AC, XF, STB, and Noise Analyses
- Virtuoso Spectre Pro S3: Transient Algorithm
- Virtuoso Spectre Pro S4: Measuring Accurate Fourier Transforms
- Virtuoso Spectre Pro S5: Transient Noise
- Virtuoso System Design Platform
- Virtuoso UltraSim Full-chip Simulator
- Virtuoso Visualization and Analysis
China Public Training Classes Schedule (2018/Q4)
All Courses Learning Map
Cadence Training Services learning maps provide a comprehensive visual overview of the learning opportunities for Cadence customers. They provide recommended course flows as well as tool experience and knowledge levels to guide students through a complete learning plan. Learning Maps cover all Cadence Technologies and reference courses available worldwide.
-
Custom IC / Analog / RF Design
-
Digital Design and Signoff
- Advanced Synthesis with Genus Stylus Common UI
- Basic Static Timing Analysis
- Cadence RTL-to-GDSII Flow
- Conformal ECO
- Conformal Equivalence Checking
- Conformal Low Power Verification Using IEEE 1801
- Conformal Low-Power Verification
- Custom Equivalence Checking with Conformal EC
- Design for Test Fundamentals
- Fundamentals of IEEE 1801 Low-Power Specification Format
- Genus Synthesis Solution
- Genus Synthesis Solution with Stylus Common UI
- Innovus Block Implementation with Stylus Common UI
- Innovus Clock Concurrent Optimization Technology for Clock Tree Synthesis
- Innovus Clock Concurrent Optimization Technology with Stylus Common UI
- Innovus Hierarchical Implementation with Stylus Common UI
- Innovus Implementation System (Block)
- Innovus Implementation System (Hierarchical)
- Innovus Low-Power Flow with Stylus Common UI
- Joules Power Calculator
- Joules Power Calculator
- Low-Power Flow with Innovus Implementation System
- Low-Power Synthesis Flow with Genus Stylus Common UI
- Modus DFT Software Solution
- Tempus Signoff Timing Analysis and Closure
- Tempus Signoff Timing Analysis and Closure with Stylus Common UI
- Test Synthesis with Genus Stylus Common UI
- Virtuoso Digital Implementation
- Voltus Power Grid Analysis and Signoff with Stylus Common UI
- Voltus Power-Grid Analysis and Signoff
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IC Package
- Allegro Package Designer
- Allegro Package Designer Plus
- Allegro Sigrity PI
- Allegro Sigrity Package Assessment and Model Extraction
- Allegro Sigrity Package Assessment and Model Extraction
- Allegro Sigrity SI Foundations
- Model Generation and Analysis using PowerSI and Broadband SPICE
- OrbitIO System Planner
- SiP Layout
- SiP Layout
- Sigrity Aurora
- Sigrity PowerDC and OptimizePI
- Sigrity PowerDC and OptimizePI (Français)
- Sigrity SystemSI for Parallel Bus and Serial Link Analysis
- TopXplorer SystemSI for Parallel Bus and Serial Link Analysis
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Languages and Methodologies
- Behavioral Modeling with VHDL-AMS
- Behavioral Modeling with Verilog-AMS
- C++ Language Fundamentals
- Essential SystemVerilog for UVM
- PCB Design at RF - Multi-Gigabit Transmission, EMI Control, and PCB Materials
- Perl for EDA Engineering
- Real Modeling with SystemVerilog
- Real Modeling with Verilog-AMS
- Specman Advanced Verification
- Specman Fundamentals for Block-Level Environment Developers
- SystemC Language Fundamentals
- SystemC Synthesis with Stratus HLS
- SystemC Transaction-Level Modeling (TLM 2.0)
- SystemVerilog Accelerated Verification with UVM
- SystemVerilog Advanced Register Verification Using UVM
- SystemVerilog Assertions
- SystemVerilog Assertions
- SystemVerilog Real Number Modeling (SV-RNM) Based Advanced Verification
- SystemVerilog for Design and Verification
- SystemVerilog for Verification
- Tcl Scripting for EDA + Intro to Tk
- VHDL Language and Application
- Verilog Language and Application
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PCB Design
- Advanced Design Verification with the RAVEL Programming Language
- Advanced PSpice for Power Users
- Allegro AMS Simulator
- Allegro AMS Simulator Advanced Analysis
- Allegro Design Entry HDL Basics
- Allegro Design Entry HDL Front-to-Back Flow
- Allegro Design Entry HDL SKILL Programming Language
- Allegro Design Entry Using OrCAD Capture
- Allegro Design Entry Using OrCAD Capture
- Allegro Design Reuse
- Allegro Design Workbench for Librarians
- Allegro EDM Design Entry HDL Front-to-Back Flow
- Allegro EDM PCB Librarian
- Allegro EDM for Administrators
- Allegro EDM for Engineers and Designers
- Allegro FPGA System Planner
- Allegro High-Speed Constraint Management
- Allegro PCB Editor Advanced Methodologies
- Allegro PCB Editor Basic Techniques
- Allegro PCB Editor Intermediate Techniques
- Allegro PCB Editor SKILL Programming Language
- Allegro PCB Librarian
- Allegro PCB Router Basics
- Allegro RF PCB
- Allegro Sigrity PI
- Allegro Sigrity SI Foundations
- Allegro System Architect
- Allegro System Capture
- Allegro Team Design Authoring
- Allegro Tool Setup and Configuration
- Allegro Update Training
- Analog Simulation with PSpice
- Analog Simulation with PSpice Advanced Analysis
- Celsius Thermal Solver
- Clarity 3D Solver
- Essential High-Speed PCB Design for Signal Integrity
- Model Generation and Analysis using PowerSI and Broadband SPICE
- OrCAD CIS
- OrCAD Capture Constraint Manager PCB Flow
- PCB Design at RF - Multi-Gigabit Transmission, EMI Control, and PCB Materials
- Sigrity Aurora
- Sigrity PowerDC and OptimizePI
- Sigrity PowerDC and OptimizePI (Français)
- Sigrity SystemSI for Parallel Bus and Serial Link Analysis
- Simulation Analogique-Mixte PSpice Avancée (Français)
- TopXplorer SystemSI for Parallel Bus and Serial Link Analysis
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System Design and Verification
- C++ Language Fundamentals
- Essential SystemVerilog for UVM
- Foundations of Metric Driven Verification
- Incisive Functional Safety Simulator
- Incisive SystemC, VHDL, and Verilog Simulation
- JasperGold Formal Expert
- JasperGold Formal Fundamentals
- Low-Power Simulation with CPF
- Low-Power Simulation with IEEE Std 1801 UPF
- Metric Driven Verification Using Cadence vManager
- Perl for EDA Engineering
- Perspec System Verifier – Basic
- Protium Rapid Prototyping Platform
- SVA, Formal and Jaspergold Fundamentals for Designers
- Specman Advanced Verification
- Specman Fundamentals for Block-Level Environment Developers
- SystemC Language Fundamentals
- SystemC Synthesis with Stratus HLS
- SystemC Transaction-Level Modeling (TLM 2.0)
- SystemVerilog Accelerated Verification with UVM
- SystemVerilog Advanced Register Verification Using UVM
- SystemVerilog Assertions
- SystemVerilog for Design and Verification
- Tcl Scripting for EDA + Intro to Tk
- VHDL Language and Application
- VIP Basic Building Blocks and Usage
- Verilog Language and Application
- Xcelium Fault Simulator
- Xcelium Integrated Coverage
- Xcelium Simulator
- vManager Tool Usage in Batch Mode
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Tensilica Processor IP
- Tensilica Audio Codec API
- Tensilica ConnX 110 and 120 DSP Family
- Tensilica ConnX B10 DSP
- Tensilica ConnX B20 DSP
- Tensilica ConnX BBE16EP Baseband Engine
- Tensilica ConnX BBE32EP Baseband Engine
- Tensilica ConnX BBE64EP Baseband Engine
- Tensilica DNA 100 Architecture and Programming
- Tensilica FloatingPoint DSP Family
- Tensilica Fusion F1 DSP
- Tensilica Fusion G3 DSP
- Tensilica Fusion G6 DSP
- Tensilica HiFi 2/EP/Mini Audio Engine ISA
- Tensilica HiFi 3 Audio Engine ISA
- Tensilica HiFi 4 DSP
- Tensilica HiFi 5 DSP
- Tensilica Instruction Extension Language and Design
- Tensilica System Modeling using XTSC
- Tensilica Vision DSP Family
- Tensilica Xtensa Audio Framework
- Tensilica Xtensa LX Hardware Verification and EDA
- Tensilica Xtensa LX Processor Fundamentals
- Tensilica Xtensa LX Processor Interfaces
- Tensilica Xtensa NX Hardware Verification and EDA
- Tensilica Xtensa NX Processor Fundamentals
- Tensilica Xtensa NX Processor Interfaces
- Tensilica Xtensa Neural Network Compiler v2
ONLINE TRAINING
Genus Synthesis Solution v16.1
This online class features the Cadence® Genus™ Synthesis Solution with next generation synthesis capabilities and how SoC design productivity gap is filled by Genus