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Cadence® 数字与签核解决方案, 提供快速的设计收敛和更出色的可预测性,助您实现功耗、性能和面积(PPA)目标。

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Multiphysics System Analysis

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嵌入式原型验证

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Cadence® PCB 设计解决方案更好地结合了组件设计和约束驱动流程的系统级仿真,实现更短、更加可预测的设计周期。

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  • 产品
    • 尖端设计工具
      • 数字设计与签核
        • PRODUCT CATEGORIES
          • 逻辑等效性检查
          • SoC Implementation and Floorplanning
          • 形式验证与功能 ECO
          • 低功耗验证
          • RTL 综合
          • 功耗分析
          • Constraints and CDC Signoff
          • 硅签核
          • 库表征
          • 可测性设计
        • FEATURED PRODUCTS
          • Cerebrus Intelligent Chip Explorer
          • Genus Synthesis Solution
          • Innovus Implementation System
          • Tempus Timing Signoff Solution
          • Pegasus Verification System
          • RESOURCES
          • Flows
          • Voltus IC Power Integrity Solution
      • 定制 IC/模拟/ RF 设计
        • PRODUCT CATEGORIES
          • 电路设计
          • 电路仿真
          • 版图设计
          • 版图验证
          • 特征库提取
          • RF / Microwave Solutions
        • FEATURED PRODUCTS
          • Spectre X Simulator
          • Spectre FX Simulator
          • Virtuoso Layout Suite
          • Virtuoso ADE Product Suite
          • Virtuoso Advanced Node
          • Voltus-Fi Custom Power Integrity Solution
          • RESOURCES
          • Flows
      • Verification
        • PRODUCT CATEGORIES
          • 调试纠错分析
          • Virtual Prototyping
          • Emulation and Prototyping
          • 形式化验证与静态验证
          • 验证规划与管理
          • 仿真
          • 软件驱动验证
          • 验证IP(VIP)
          • System-Level Verification IP
        • FEATURED PRODUCTS
          • vManager Verification Management
          • Xcelium Logic Simulation
          • Palladium Enterprise Emulation
          • Protium Enterprise Prototyping
          • System VIP
          • RESOURCES
          • Flows
          • Jasper C Apps
          • Helium Virtual and Hybrid Studio
      • IP
        • PRODUCT CATEGORIES
          • Denali Memory Interface and Storage IP
          • 112G/56G SerDes
          • PCIe and CXL
          • Tensilica Processor IP
          • Chiplet and D2D
          • Interface IP
        • RESOURCES
          • Discover PCIe
      • IC 封装设计与分析
        • PRODUCT CATEGORIES
          • IC 封装设计
          • IC封装设计流程
          • SI/PI 分析
          • SI/PI 分析点工具
          • 跨平台协同设计与分析
    • 创新系统设计
      • Multiphysics System Analysis
        • PRODUCT CATEGORIES
          • Computational Fluid Dynamics
          • 电磁求解器
          • 射频/微波设计
          • Signal and Power Integrity
          • 热求解器
        • FEATURED PRODUCTS
          • Clarity 3D Solver
          • Clarity 3D Solver Cloud
          • Clarity 3D Transient Solver
          • Celsius Thermal Solver
          • Fidelity CFD
          • Sigrity Advanced SI
          • Celsius Advanced PTI
          • RESOURCES
          • System Analysis Center
          • System Analysis Resources Hub
          • AWR Free Trial
      • 嵌入式原型验证
      • PCB 设计与分析
        • PRODUCT CATEGORIES
          • 原理图设计
          • PCB Layout
          • 库与设计数据管理
          • 模拟/混合信号仿真
          • SI/PI Analysis
          • SI/PI 分析点工具
          • 射频/微波设计
          • Augmented Reality Lab Tools
        • FEATURED PRODUCTS
          • Allegro Package Designer Plus
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          • RESOURCES
          • What's New in Allegro
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  • Custom IC / Analog / RF Design (70)
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Cadence Training Services learning maps provide a comprehensive visual overview of the learning opportunities for Cadence customers. They provide recommended course flows as well as tool experience and knowledge levels to guide students through a complete learning plan. Learning Maps cover all Cadence Technologies and reference courses available worldwide.

  • Custom IC / Analog / RF Design
    • 5G mmWave Handset System Design – S1: RFIC (Transceiver) Design
    • Advanced SKILL Language Programming
    • Analog Modeling and Simulation with SPICE
    • Analog Modeling with Verilog-A
    • Behavioral Modeling with VHDL-AMS
    • Behavioral Modeling with Verilog-AMS
    • Command-Line Based Mixed-Signal Simulations with the Xcelium Use Model
    • Design Checks and Asserts
    • High-Performance Spectre Simulation
    • Mixed Signal Simulations Using Spectre AMS Designer
    • Mixed Signal Simulations Using Spectre AMS Designer
    • Pegasus Verification System
    • Pegasus Verification System
    • Physical Verification Language Rules Writer
    • Physical Verification System
    • Physical Verification System
    • Quantus Transistor-Level T1: Overview and Technology Setup
    • Quantus Transistor-Level T1: Overview and Technology Setup
    • Quantus Transistor-Level T2: Parasitic Extraction
    • Quantus Transistor-Level T2: Parasitic Extraction
    • Quantus Transistor-Level T3: Extracted View Flows and Advanced Features
    • Quantus Transistor-Level T3: Extracted View Flows and Advanced Features
    • Real Modeling with SystemVerilog
    • Real Modeling with SystemVerilog
    • Real Modeling with Verilog-AMS
    • SKILL Development of Parameterized Cells
    • SKILL Language Programming
    • SKILL Language Programming Fundamentals
    • SKILL Language Programming Introduction
    • SKILL Language Programming Introduction
    • Simulation and Analysis Using OCEAN
    • Simulation and Analysis Using OCEAN
    • Spectre Accelerated Parallel Simulator
    • Spectre Accelerated Parallel Simulator
    • Spectre RF Analysis using Harmonic Balance
    • Spectre RF Analysis using Shooting Newton Method
    • Spectre Simulator Fundamentals S1: Spectre Basics
    • Spectre Simulator Fundamentals S2: Large-Signal Analyses
    • Spectre Simulator Fundamentals S3: Small-Signal Analyses
    • Spectre Simulator Fundamentals S3: Small-Signal Analyses
    • Spectre Simulator Fundamentals S4: Measurement Description Language
    • Spectre Simulator Fundamentals S4: Measurement Description Language
    • Spectre eXtensive Partitioning Simulator for Mixed-Signal Designs
    • SystemVerilog Real Number Modeling (SV-RNM) Based Advanced Verification
    • Variation Analysis Using the Virtuoso Variation Option
    • Virtuoso ADE Explorer and Assembler S1: ADE Explorer and Single Test Corner Analysis
    • Virtuoso ADE Explorer and Assembler S2: ADE Assembler and Multi Test Corner Analysis
    • Virtuoso ADE Explorer and Assembler S3: Sweeping Variables and Simulating Corners
    • Virtuoso ADE Explorer and Assembler S4: Monte Carlo Analysis, Real-Time Tuning and Run Plans
    • Virtuoso ADE Verifier S1: Setup, Run and View Verification Results
    • Virtuoso ADE Verifier S2: Reference Flow and Analog Coverage Using the Setup Library Assistant
    • Virtuoso Abstract Generator
    • Virtuoso Analog Design Environment
    • Virtuoso Analog Simulation: T1 The Virtuoso Analog Design XL Environment
    • Virtuoso Analog Simulation: T2 Creating Sweeps and Running Corner Analysis
    • Virtuoso Analog Simulation: T3 Monte Carlo Simulations Using ADEXL
    • Virtuoso Analog Simulation: T4 Sensitivity Analysis and Circuit Optimization Using ADE(G)XL
    • Virtuoso Connectivity-Driven Layout Transition
    • Virtuoso Floorplanner
    • Virtuoso Layout Design Basics
    • Virtuoso Layout Pro: T1 Environment and Basic Commands (L)
    • Virtuoso Layout Pro: T2 Create and Edit Commands (L)
    • Virtuoso Layout Pro: T3 Basic Commands (XL)
    • Virtuoso Layout Pro: T4 Advanced Commands (XL)
    • Virtuoso Layout Pro: T5 Interactive Routing (XL)
    • Virtuoso Layout Pro: T6 Constraint-Driven Flow and Power Routing
    • Virtuoso Layout Pro: T7 Module Generator and Floorplanner (XL/GXL)
    • Virtuoso Layout Pro: T9 Virtuoso Design Planner
    • Virtuoso Layout for Advanced Nodes
    • Virtuoso Layout for Advanced Nodes and Methodology Platform
    • Virtuoso Layout for Advanced Nodes and Methodology Platform
    • Virtuoso Layout for Advanced Nodes: T1 Place and Route
    • Virtuoso Layout for Advanced Nodes: T2 Electromigration
    • Virtuoso Schematic Editor
    • Virtuoso Simulation Driven Routing (SDR)
    • Virtuoso Spectre Pro S1: DC Algorithm
    • Virtuoso Spectre Pro S2: AC, XF, STB, and Noise Analyses
    • Virtuoso Spectre Pro S3: Transient Algorithm
    • Virtuoso Spectre Pro S4: Measuring Accurate Fourier Transforms
    • Virtuoso Spectre Pro S5: Transient Noise
    • Virtuoso System Design Platform
    • Virtuoso UltraSim Full-chip Simulator
    • Virtuoso Visualization and Analysis
  • Digital Design and Signoff
    • Advanced Synthesis with Genus Stylus Common UI
    • Basic Static Timing Analysis
    • Cadence RTL-to-GDSII Flow
    • Conformal ECO
    • Conformal Equivalence Checking
    • Conformal Low Power Verification Using IEEE 1801
    • Conformal Low-Power Verification
    • Custom Equivalence Checking with Conformal EC
    • Design for Test Fundamentals
    • Fundamentals of IEEE 1801 Low-Power Specification Format
    • Genus Synthesis Solution
    • Genus Synthesis Solution with Stylus Common UI
    • Innovus Block Implementation with Stylus Common UI
    • Innovus Clock Concurrent Optimization Technology for Clock Tree Synthesis
    • Innovus Clock Concurrent Optimization Technology with Stylus Common UI
    • Innovus Hierarchical Implementation with Stylus Common UI
    • Innovus Implementation System (Block)
    • Innovus Implementation System (Hierarchical)
    • Innovus Low-Power Flow with Stylus Common UI
    • Joules Power Calculator
    • Joules Power Calculator
    • Low-Power Flow with Innovus Implementation System
    • Low-Power Synthesis Flow with Genus Stylus Common UI
    • Modus DFT Software Solution
    • Tempus Signoff Timing Analysis and Closure
    • Tempus Signoff Timing Analysis and Closure with Stylus Common UI
    • Test Synthesis with Genus Stylus Common UI
    • Virtuoso Digital Implementation
    • Voltus Power Grid Analysis and Signoff with Stylus Common UI
    • Voltus Power-Grid Analysis and Signoff
  • IC Package
    • Allegro Package Designer
    • Allegro Package Designer Plus
    • Allegro Sigrity PI
    • Allegro Sigrity Package Assessment and Model Extraction
    • Allegro Sigrity Package Assessment and Model Extraction
    • Allegro Sigrity SI Foundations
    • Model Generation and Analysis using PowerSI and Broadband SPICE
    • OrbitIO System Planner
    • SiP Layout
    • SiP Layout
    • Sigrity Aurora
    • Sigrity PowerDC and OptimizePI
    • Sigrity PowerDC and OptimizePI (Français)
    • Sigrity SystemSI for Parallel Bus and Serial Link Analysis
    • TopXplorer SystemSI for Parallel Bus and Serial Link Analysis
  • Languages and Methodologies
    • Behavioral Modeling with VHDL-AMS
    • Behavioral Modeling with Verilog-AMS
    • C++ Language Fundamentals
    • Essential SystemVerilog for UVM
    • PCB Design at RF - Multi-Gigabit Transmission, EMI Control, and PCB Materials
    • Perl for EDA Engineering
    • Real Modeling with SystemVerilog
    • Real Modeling with Verilog-AMS
    • Specman Advanced Verification
    • Specman Fundamentals for Block-Level Environment Developers
    • SystemC Language Fundamentals
    • SystemC Synthesis with Stratus HLS
    • SystemC Transaction-Level Modeling (TLM 2.0)
    • SystemVerilog Accelerated Verification with UVM
    • SystemVerilog Advanced Register Verification Using UVM
    • SystemVerilog Assertions
    • SystemVerilog Assertions
    • SystemVerilog Real Number Modeling (SV-RNM) Based Advanced Verification
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