China Public Training Classes Schedule (2018/Q4)
All Courses Learning Map
Cadence Training Services learning maps provide a comprehensive visual overview of the learning opportunities for Cadence customers. They provide recommended course flows as well as tool experience and knowledge levels to guide students through a complete learning plan. Learning Maps cover all Cadence Technologies and reference courses available worldwide.
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Custom IC / Analog / RF Design
- Accelerate Design Productivity with Virtuoso ADE Explorer and Assembler
- Analog Modeling and Simulation with SPICE
- Analog Modeling with Verilog-A
- Assura Parasitic Extraction (RCX)
- Assura RCX Developer
- Assura Rules Writer
- Assura Verification
- Behavioral Modeling with VHDL-AMS
- Behavioral Modeling with Verilog-AMS
- Cadence QRC Techgen Developer
- Command-Line Based Mixed-Signal Simulations with the Xcelium Use Model
- MaskCompose Automated Reticle Design Synthesis
- Mixed Signal Simulations Using AMS Designer
- Mixed Signal Simulations Using Spectre AMS Designer
- Pegasus Verification System
- Physical Verification Language Rules Writer
- Physical Verification System
- Quantus Transistor-Level T1: Overview and Technology Setup
- Quantus Transistor-Level T2: Parasitic Extraction
- Quantus Transistor-Level T3: Extracted View Flows and Advanced Features
- SKILL Development of Parameterized Cells
- SKILL Language Programming
- SKILL Language Programming Introduction
- SKILL Programming for IC Layout Design
- Simulation and Analysis Using OCEAN
- Spectre Accelerated Parallel Simulator
- Spectre Simulator Fundamentals S1: Spectre Basics
- Spectre Simulator Fundamentals S2: Large-Signal Analyses
- Spectre Simulator Fundamentals S3: Small-Signal Analyses
- Spectre Simulator Fundamentals S4: Measurement Description Language
- Transistor Level Power Signoff with Voltus-Fi
- Using Virtuoso Constraints Effectively
- Virtuoso ADE Assembler S3: Circuit Checks, Device Asserts, and Reliability Analysis
- Virtuoso ADE Explorer and Assembler S1: ADE Explorer and Single Test Corner Analysis
- Virtuoso ADE Explorer and Assembler S2: ADE Assembler and Multi Test Corner Analysis
- Virtuoso ADE Explorer and Assembler S3: Sweeping Variables and Simulating Corners
- Virtuoso ADE Verifier S1: Setup, Run and View Verification Results
- Virtuoso AMS Designer
- Virtuoso Analog Design Environment
- Virtuoso Analog Simulation: T2 Creating Sweeps and Running Corner Analysis
- Virtuoso Analog Simulation: T3 Monte Carlo Simulations Using ADEXL
- Virtuoso Analog Simulation: T4 Sensitivity Analysis and circuit Optimization Using ADE(G)XL
- Virtuoso Connectivity-Driven Layout Transition
- Virtuoso Electrically-Aware Design with Layout-Dependent Effects
- Virtuoso Floorplanner
- Virtuoso Layout Pro: T1 Environment and Basic Commands (L)
- Virtuoso Layout Pro: T3 Basic Commands (XL)
- Virtuoso Layout Pro: T4 Advanced Commands (XL)
- Virtuoso Layout Pro: T7 Module Generator and Floorplanner (XL/GXL)
- Virtuoso Layout Pro: T8 Debugging Layout Issues
- Virtuoso Online Training Course Collection
- Virtuoso Schematic Editor
- Virtuoso Space-based Router
- Virtuoso Spectre Pro S1: DC Algorithm
- Virtuoso Spectre Pro S2: AC, XF, STB, and Noise Analyses
- Virtuoso Spectre Pro S3: Transient Algorithm
- Virtuoso Spectre Pro S4: Measuring Accurate Fourier Transforms
- Virtuoso Spectre Pro S5: Transient Noise
- Virtuoso System Design Platform
- Virtuoso UltraSim Full-chip Simulator
- Virtuoso Visualization and Analysis
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Digital Design and Signoff
- Advanced Synthesis with Genus Synthesis Solution
- Conformal Low-Power Verification
- Fundamentals of IEEE 1801 Low-Power Specification Format
- Genus Synthesis Solution
- Innovus Clock Concurrent Optimization Technology for Clock Tree Synthesis
- Innovus Clock Concurrent Optimization Technology with Stylus Common UI
- Innovus Implementation System (Block)
- Innovus Implementation System (Hierarchical)
- Joules™ Power Calculator
- Low-Power Flow with Innovus Implementation System
- Low-Power Synthesis Flow with Genus Synthesis Solution
- Modus DFT Software Solution
- Tempus Signoff Timing Analysis and Closure
- Test Synthesis Using Genus Synthesis Solution
- Test Synthesis with Genus Stylus Common UI
- Virtuoso ADE Verifier S1: Setup, Run and View Verification Results
- Virtuoso Digital Implementation
- Voltus Power Grid Analysis and Signoff with Stylus Common UI
- Voltus Power-Grid Analysis and Signoff
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IC Package
- Allegro Sigrity PI
- Allegro Sigrity Package Assessment and Model Extraction
- Allegro Sigrity Package Assessment and Model Extraction
- Allegro Sigrity Power-Aware Parallel Bus Analysis
- Allegro Sigrity Power-Aware Parallel Bus Analysis
- Allegro Sigrity SI Foundations
- Improving SI/PI Simulation of DDR Interfaces at the PCB/IC Package Level (Webinar)
- Model Generation and Analysis using PowerSI, Broadband SPICE and 3D-EM
- OrbitIO System Planner
- Power Distribution Network Fundamentals for Design and PCB Layout (Webinar)
- SiP Layout
- SiP Layout
- Sigrity PowerDC and OptimizePI
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Languages and Methodologies
- Behavioral Modeling with VHDL-AMS
- Behavioral Modeling with Verilog-AMS
- Perl for EDA Engineering
- Real Modeling with SystemVerilog
- Specman Advanced Verification
- Specman Fundamentals for Block-Level Environment Developers
- SystemC Transaction-Level Modeling (TLM 2.0)
- SystemVerilog Accelerated Verification with UVM
- SystemVerilog Advanced Register Verification Using UVM
- SystemVerilog for Design and Verification
- SystemVerilog for Verification
- Tcl Scripting for EDA
- VHDL Language and Application
- Verilog for VHDL Users
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PCB Design
- Advanced PSpice for Power Users
- Allegro AMS Simulator Advanced Analysis
- Allegro Design Entry HDL Basics
- Allegro Design Entry HDL Front-to-Back Flow
- Allegro Design Entry HDL SKILL Programming Language
- Allegro Design Entry Using OrCAD Capture
- Allegro Design Workbench for Librarians
- Allegro EDM PCB Librarian
- Allegro EDM for Administrators
- Allegro EDM for Engineers and Designers
- Allegro FPGA System Planner
- Allegro High-Speed Constraint Management
- Allegro PCB Editor Basic Techniques
- Allegro PCB Editor Intermediate Techniques
- Allegro PCB Librarian
- Allegro PCB Router Basics
- Allegro RF PCB
- Allegro Sigrity PI
- Allegro Sigrity Power-Aware Parallel Bus Analysis
- Allegro Sigrity Power-Aware Parallel Bus Analysis
- Allegro Sigrity SI Foundations
- Allegro System Architect
- Allegro Team Design Authoring
- Allegro Tool Setup and Configuration
- Analog Simulation with PSpice
- Celsius Thermal Solver
- Clarity 3D Solver
- Model Generation and Analysis using PowerSI, Broadband SPICE and 3D-EM
- OrCAD Capture Constraint Manager PCB Flow
- Sigrity PowerDC and OptimizePI
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System Design and Verification
- Comprehensive RTL Signoff by Designers Using JasperGold Superlint
- Creating Assertions for SV Real-number Modeling (Webinar)
- Foundations of Metric Driven Verification
- Incisive Functional Safety Simulator
- Incisive SystemC, VHDL, and Verilog Simulation
- Low-Power Simulation with CPF
- Metric Driven Verification using Cadence vManager
- Perl for EDA Engineering
- Protium Rapid Prototyping Platform
- SVA, Formal and JasperGold® Fundamentals for Designers
- Specman Advanced Verification
- Specman Fundamentals for Block-Level Environment Developers
- SystemC Transaction-Level Modeling (TLM 2.0)
- SystemVerilog Accelerated Verification with UVM
- SystemVerilog Advanced Register Verification Using UVM
- SystemVerilog for Design and Verification
- SystemVerilog for Verification
- Tcl Scripting for EDA
- VHDL Language and Application
- Verilog for VHDL Users
- Xcelium Simulator
- vManager Tool Usage in Batch Mode
SELF PACED ONLINE TRAINING
Online Training Subscription
Multiple online courses of one or more technology groups, for 12 months unlimited, per student
ONLINE TRAINING
Genus Synthesis Solution v16.1
This online class features the Cadence® Genus™ Synthesis Solution with next generation synthesis capabilities and how SoC design productivity gap is filled by Genus