Home
  • 产品
  • 解决方案
  • 支持与培训
  • 公司
  • ZH CN
    • SELECT YOUR COUNTRY OR REGION

    • US - English
    • Japan - 日本語
    • Korea - 한국어
    • Taiwan - 繁體中文

尖端设计工具

  • 数字设计与签核
  • 定制 IC/模拟/ RF 设计
  • 系统设计与验证
  • IP
  • IC 封装设计与分析

创新系统设计

  • 系统分析
  • 嵌入式原型验证
  • PCB 设计与分析

万物智能

  • AI / 机器学习
  • AI IP 产品

CADENCE云服务

数字设计与签核

Cadence® 数字与签核解决方案, 提供快速的设计收敛和更出色的可预测性,助您实现功耗、性能和面积(PPA)目标。

  • 逻辑等效性检查
  • Innovus实现和布图规划
  • 形式验证与功能 ECO
  • 低功耗验证
  • RTL 综合
  • 功耗分析
  • 约束和CDC签核
  • 硅签核
  • 库表征
  • 可测性设计
  • 数字流程
  • Achieve best PPA with the next-generation Digital Full Flow solution Learn More
  • Address digital implementation challenges with machine learning Watch Now

定制 IC/模拟/ RF 设计

Cadence® 定制、模拟和射频设计解决方案可以实现模块级和混合信号仿真、布线和特征参数提取等诸多日常任务的自动化,助您节省大量时间。

  • 电路设计
  • 电路仿真
  • 版图设计
  • 版图验证
  • 特征库提取
  • RF / Microwave Solutions
  • 定制、模拟、射频集成电路设计流程
  • Solve analog simulation challenges in complex designs Watch Now
  • See how the Virtuoso Design Platform addresses advanced custom IC and system design challenges Watch Now

系统设计与验证

Cadence® Verification Suite中的系统设计和验证解决方案提供仿真、加速、模拟和验证管理功能。

  • 调试纠错分析
  • 硬件仿真加速器
  • 形式化验证与静态验证
  • FPGA 原型验证
  • 验证规划与管理
  • 仿真
  • 软件驱动验证
  • 验证IP(VIP)
  • System-Level Verification IP
  • 系统设计和验证流程
  • Prototype your embedded software development Watch Now
  • Learn how early firmware development enabled first silicon success at Toshiba Memory Watch Now

IP

开放的 IP 平台助您定制应用驱动的系统级芯片(SoC)设计。

  • Interface IP
  • Denali Memory IP
  • Tensilica 处理器 IP
  • Analog IP
  • System / Peripherals IP
  • 验证 IP
  • Solve the challenges of long-reach signaling with Cadence 112G SerDes IP Watch Now
  • Meeting the needs of 5G communication with Tensilica® ConnX B20 DSP IP Download Now

IC 封装设计与分析

提升先进封装、系统规划和多织构互操作性的效率和准确性,Cadence 封装实现工具可实现自动化和精准度。

  • 跨平台协同设计与分析
  • IC 封装设计
  • SI/PI 分析
  • SI/PI 分析点工具
  • IC封装设计流程
  • Cadence Design Solutions certified for TSMC SoIC advanced 3D chip stacking technology Learn More
  • Four reasons to avoid multi-layer flip-chip pin padstacks Learn More

系统分析

Cadence®系统分析解决方案提供高精度的电磁提取和仿真分析,确保您的系统在广泛的运行条件下正常工作。

  • See how to improve electrical-thermal co-simulation with the Celsius™ Thermal Solver Watch Now
  • Get true 3D system analysis with faster speeds, more capacity, and integration Watch Now
  • 电磁求解器
  • 射频/微波设计
  • 热求解器
  • System Analysis Resources Hub

嵌入式原型验证

PCB 设计与分析

Cadence® PCB 设计解决方案更好地结合了组件设计和约束驱动流程的系统级仿真,实现更短、更加可预测的设计周期。

  • 原理图设计
  • PCB 版图设计
  • 库与设计数据管理
  • 模拟/混合信号仿真
  • SI/PI 分析
  • SI/PI 分析点工具
  • Allegro最新技术
  • Sigrity最新技术
  • 射频/微波设计
  • PCB 设计与分析流程
  • Advanced PCB Design & Analysis Blog
  • Watch how to easily tackle complex and cutting edge designs. Learn More
  • Learn why signal integrity analysis needs to be power-aware Watch Now
  • Augmented Reality Lab Tools

AI / 机器学习

AI IP 产品

产业方案

  • 5G系统与子系统
  • 航天与国防
  • 汽车电子解决方案
  • AI / 机器学习

技术方案

  • 3D-IC设计
  • 数字先进节点
  • Arm-Based解决方案
  • Cloud 解决方案
  • 低功耗设计
  • 混合信号设计
  • 光电设计
  • 射频/微波
See how our customers create innovative products with Cadence Explore Now

技术支持

  • 技术支持流程
  • 线上技术支持
  • 软件下载
  • 计算平台支持
  • 售后支持联络
  • 技术论坛

培训

  • 定制IC/模拟/设计
  • 设计语言及方法学
  • 数字设计与签核
  • IC封装
  • PCB设计
  • 系统设计与验证
Stay up to date with the latest software Download Now
24/7 - Cadence Online Support Visit Now

公司介绍

  • 关于我们
  • 成功合作
  • 投资者关系
  • 管理团队
  • Computational Software
  • Alliances
  • 公司社会责任
  • Cadence大学计划

媒体中心

  • 会议活动
  • 新闻中心
  • 博客

企业文化与职业

  • Cadence文化与多样性
  • 招贤纳士
Learn how Intelligent System Design™ powers future technologies Learn More
Browse Cadence’s latest on-demand sessions and upcoming events. Explore More
View all Products
  • 产品
    • 尖端设计工具
      • 数字设计与签核
        • 逻辑等效性检查
        • Innovus实现和布图规划
        • 形式验证与功能 ECO
        • 低功耗验证
        • RTL 综合
        • 功耗分析
        • 约束和CDC签核
        • 硅签核
        • 库表征
        • 可测性设计
        • 数字流程
      • 定制 IC/模拟/ RF 设计
        • 电路设计
        • 电路仿真
        • 版图设计
        • 版图验证
        • 特征库提取
        • RF / Microwave Solutions
        • 定制、模拟、射频集成电路设计流程
      • 系统设计与验证
        • 调试纠错分析
        • 硬件仿真加速器
        • 形式化验证与静态验证
        • FPGA 原型验证
        • 验证规划与管理
        • 仿真
        • 软件驱动验证
        • 验证IP(VIP)
        • System-Level Verification IP
        • 系统设计和验证流程
      • IP
        • Interface IP
        • Denali Memory IP
        • Tensilica 处理器 IP
        • Analog IP
        • System / Peripherals IP
        • 验证 IP
      • IC 封装设计与分析
        • 跨平台协同设计与分析
        • IC 封装设计
        • SI/PI 分析
        • SI/PI 分析点工具
        • IC封装设计流程
    • 创新系统设计
      • 系统分析
        • 电磁求解器
        • 射频/微波设计
        • 热求解器
        • System Analysis Resources Hub
      • 嵌入式原型验证
      • PCB 设计与分析
        • 原理图设计
        • PCB 版图设计
        • 库与设计数据管理
        • 模拟/混合信号仿真
        • SI/PI 分析
        • SI/PI 分析点工具
        • Allegro最新技术
        • Sigrity最新技术
        • 射频/微波设计
        • PCB 设计与分析流程
        • Advanced PCB Design & Analysis Blog
        • Augmented Reality Lab Tools
    • 万物智能
      • AI / 机器学习
      • AI IP 产品
    • CADENCE云服务
  • 解决方案
      • 产业方案
        • 5G系统与子系统
        • 航天与国防
        • 汽车电子解决方案
        • AI / 机器学习
      • 技术方案
        • 3D-IC设计
        • 数字先进节点
        • Arm-Based解决方案
        • Cloud 解决方案
        • 低功耗设计
        • 混合信号设计
        • 光电设计
        • 射频/微波
      • 产业方案
        • 5G系统与子系统
        • 航天与国防
        • 汽车电子解决方案
        • AI / 机器学习
      • 技术方案
        • 3D-IC设计
        • 数字先进节点
        • Arm-Based解决方案
        • Cloud 解决方案
        • 低功耗设计
        • 混合信号设计
        • 光电设计
        • 射频/微波
      • 产业方案
        • 5G系统与子系统
        • 航天与国防
        • 汽车电子解决方案
        • AI / 机器学习
      • 技术方案
        • 3D-IC设计
        • 数字先进节点
        • Arm-Based解决方案
        • Cloud 解决方案
        • 低功耗设计
        • 混合信号设计
        • 光电设计
        • 射频/微波
      • 产业方案
        • 5G系统与子系统
        • 航天与国防
        • 汽车电子解决方案
        • AI / 机器学习
      • 技术方案
        • 3D-IC设计
        • 数字先进节点
        • Arm-Based解决方案
        • Cloud 解决方案
        • 低功耗设计
        • 混合信号设计
        • 光电设计
        • 射频/微波
  • 支持与培训
      • 技术支持
        • 技术支持流程
        • 线上技术支持
        • 软件下载
        • 计算平台支持
        • 售后支持联络
        • 技术论坛
      • 培训
        • 定制IC/模拟/设计
        • 设计语言及方法学
        • 数字设计与签核
        • IC封装
        • PCB设计
        • 系统设计与验证
      • 技术支持
        • 技术支持流程
        • 线上技术支持
        • 软件下载
        • 计算平台支持
        • 售后支持联络
        • 技术论坛
      • 培训
        • 定制IC/模拟/设计
        • 设计语言及方法学
        • 数字设计与签核
        • IC封装
        • PCB设计
        • 系统设计与验证
      • 技术支持
        • 技术支持流程
        • 线上技术支持
        • 软件下载
        • 计算平台支持
        • 售后支持联络
        • 技术论坛
      • 培训
        • 定制IC/模拟/设计
        • 设计语言及方法学
        • 数字设计与签核
        • IC封装
        • PCB设计
        • 系统设计与验证
      • 技术支持
        • 技术支持流程
        • 线上技术支持
        • 软件下载
        • 计算平台支持
        • 售后支持联络
        • 技术论坛
      • 培训
        • 定制IC/模拟/设计
        • 设计语言及方法学
        • 数字设计与签核
        • IC封装
        • PCB设计
        • 系统设计与验证
  • 公司
      • 公司介绍
        • 关于我们
        • 成功合作
        • 投资者关系
        • 管理团队
        • Computational Software
        • Alliances
        • 公司社会责任
        • Cadence大学计划
      • 媒体中心
        • 会议活动
        • 新闻中心
        • 博客
      • 企业文化与职业
        • Cadence文化与多样性
        • 招贤纳士
      • 公司介绍
        • 关于我们
        • 成功合作
        • 投资者关系
        • 管理团队
        • Computational Software
        • Alliances
        • 公司社会责任
        • Cadence大学计划
      • 媒体中心
        • 会议活动
        • 新闻中心
        • 博客
      • 企业文化与职业
        • Cadence文化与多样性
        • 招贤纳士
      • 公司介绍
        • 关于我们
        • 成功合作
        • 投资者关系
        • 管理团队
        • Computational Software
        • Alliances
        • 公司社会责任
        • Cadence大学计划
      • 媒体中心
        • 会议活动
        • 新闻中心
        • 博客
      • 企业文化与职业
        • Cadence文化与多样性
        • 招贤纳士
      • 公司介绍
        • 关于我们
        • 成功合作
        • 投资者关系
        • 管理团队
        • Computational Software
        • Alliances
        • 公司社会责任
        • Cadence大学计划
      • 媒体中心
        • 会议活动
        • 新闻中心
        • 博客
      • 企业文化与职业
        • Cadence文化与多样性
        • 招贤纳士

  • Home
  •   :  
  • Training
  •   :  
  • All Courses

All Courses

  • Menu
  • 概览
  • 培训方法
    • Instructor-Led Training
    • Online Training
  • 全球资讯
    • Asia Pacific
    • 中国培训
    • 印度
    • 新加坡
    • 日本
    • 韩国
    • 台湾
    • EMEA
    • 法国
    • 德国
    • 以色列
    • 意大利
    • 俄罗斯
    • 瑞典
    • 英国
    • North America
    • Ottawa, ON
    • Austin, TX
    • Burlington, MA
    • San Jose, CA
  • Custom IC / Analog / RF Design (75)
  • Digital Design and Signoff (31)
  • IC Package (13)
  • Languages and Methodologies (22)
  • PCB Design (48)
  • System Design and Verification (32)
  • Tensilica Processor IP (27)
  • All Courses (218)

China Public Training Classes Schedule (2018/Q4)

All Courses Learning Map

Cadence Training Services learning maps provide a comprehensive visual overview of the learning opportunities for Cadence customers. They provide recommended course flows as well as tool experience and knowledge levels to guide students through a complete learning plan. Learning Maps cover all Cadence Technologies and reference courses available worldwide.

  • Custom IC / Analog / RF Design
    • 5G mmWave Handset System Design – S1: RFIC (Transceiver) Design
    • Advanced SKILL Language Programming
    • Analog Modeling and Simulation with SPICE
    • Analog Modeling with Verilog-A
    • Assura Parasitic Extraction (RCX)
    • Assura RCX Developer
    • Assura Rules Writer
    • Assura Verification
    • Behavioral Modeling with VHDL-AMS
    • Behavioral Modeling with Verilog-AMS
    • Command-Line Based Mixed-Signal Simulations with the Xcelium Use Model
    • Design Checks and Asserts
    • Mixed Signal Simulations Using Spectre AMS Designer
    • Mixed Signal Simulations Using Spectre AMS Designer
    • Pegasus Verification System
    • Pegasus Verification System
    • Physical Verification Language Rules Writer
    • Physical Verification System
    • Quantus Transistor-Level T1: Overview and Technology Setup
    • Quantus Transistor-Level T2: Parasitic Extraction
    • Quantus Transistor-Level T3: Extracted View Flows and Advanced Features
    • Real Modeling with SystemVerilog
    • Real Modeling with SystemVerilog
    • Real Modeling with Verilog-AMS
    • SKILL Development of Parameterized Cells
    • SKILL Language Programming
    • SKILL Language Programming Fundamentals
    • SKILL Language Programming Introduction
    • SKILL Language Programming Introduction
    • Simulation and Analysis Using OCEAN
    • Spectre Accelerated Parallel Simulator
    • Spectre Accelerated Parallel Simulator
    • Spectre Simulator Fundamentals S1: Spectre Basics
    • Spectre Simulator Fundamentals S2: Large-Signal Analyses
    • Spectre Simulator Fundamentals S3: Small-Signal Analyses
    • Spectre Simulator Fundamentals S3: Small-Signal Analyses
    • Spectre Simulator Fundamentals S4: Measurement Description Language
    • Spectre Simulator Fundamentals S4: Measurement Description Language
    • Spectre eXtensive Partitioning Simulator for Mixed-Signal Designs
    • Spectre® RF Analysis using Harmonic Balance
    • Spectre® RF Analysis using Shooting Newton Method
    • SystemVerilog Real Number Modeling (SV-RNM) Based Advanced Verification
    • Variation Analysis Using the Virtuoso Variation Option
    • Virtuoso ADE Explorer and Assembler S1: ADE Explorer and Single Test Corner Analysis
    • Virtuoso ADE Explorer and Assembler S2: ADE Assembler and Multi Test Corner Analysis
    • Virtuoso ADE Explorer and Assembler S3: Sweeping Variables and Simulating Corners
    • Virtuoso ADE Explorer and Assembler S4: Monte Carlo Analysis, Real-Time Tuning and Run Plans
    • Virtuoso ADE Verifier S1: Setup, Run and View Verification Results
    • Virtuoso ADE Verifier S2: Reference Flow and Analog Coverage Using the Setup Library Assistant
    • Virtuoso Abstract Generator
    • Virtuoso Analog Design Environment
    • Virtuoso Analog Simulation: T1 The Virtuoso Analog Design XL Environment
    • Virtuoso Analog Simulation: T2 Creating Sweeps and Running Corner Analysis
    • Virtuoso Analog Simulation: T3 Monte Carlo Simulations Using ADEXL
    • Virtuoso Analog Simulation: T4 Sensitivity Analysis and Circuit Optimization Using ADE(G)XL
    • Virtuoso Connectivity-Driven Layout Transition
    • Virtuoso Floorplanner
    • Virtuoso Layout Design Basics
    • Virtuoso Layout Pro: T1 Environment and Basic Commands (L)
    • Virtuoso Layout Pro: T2 Create and Edit Commands (L)
    • Virtuoso Layout Pro: T3 Basic Commands (XL)
    • Virtuoso Layout Pro: T4 Advanced Commands (XL)
    • Virtuoso Layout Pro: T5 Interactive Routing (XL)
    • Virtuoso Layout Pro: T6 Constraint-Driven Flow and Power Routing
    • Virtuoso Layout Pro: T7 Module Generator and Floorplanner (XL/GXL)
    • Virtuoso Layout Pro: T8 Debugging Layout Issues
    • Virtuoso Layout Pro: T9 Virtuoso Design Planner
    • Virtuoso Layout for Advanced Nodes
    • Virtuoso Layout for Advanced Nodes and Methodology Platform
    • Virtuoso Layout for Advanced Nodes and Methodology Platform
    • Virtuoso Layout for Advanced Nodes: T1 Place and Route
    • Virtuoso Layout for Advanced Nodes: T2 Electromigration
    • Virtuoso Schematic Editor
    • Virtuoso Space-Based Router
    • Virtuoso Space-Based Router Express
    • Virtuoso Spectre Pro S1: DC Algorithm
    • Virtuoso Spectre Pro S1: DC Algorithm
    • Virtuoso Spectre Pro S2: AC, XF, STB, and Noise Analyses
    • Virtuoso Spectre Pro S3: Transient Algorithm
    • Virtuoso Spectre Pro S4: Measuring Accurate Fourier Transforms
    • Virtuoso Spectre Pro S5: Transient Noise
    • Virtuoso System Design Platform
    • Virtuoso UltraSim Full-chip Simulator
    • Virtuoso Visualization and Analysis
  • Digital Design and Signoff
    • Advanced Synthesis with Genus Stylus Common UI
    • Advanced Synthesis with Genus Synthesis Solution
    • Basic Static Timing Analysis
    • Cadence RTL-to-GDSII Flow
    • Conformal ECO
    • Conformal ECO
    • Conformal Equivalence Checking
    • Conformal Low-Power Verification
    • Custom Equivalence Checking with Conformal EC
    • Design for Test Fundamentals
    • Fundamentals of IEEE 1801 Low-Power Specification Format
    • Genus Synthesis Solution
    • Genus Synthesis Solution with Stylus Common UI
    • Innovus Block Implementation with Stylus Common UI
    • Innovus Clock Concurrent Optimization Technology for Clock Tree Synthesis
    • Innovus Clock Concurrent Optimization Technology with Stylus Common UI
    • Innovus Hierarchical Implementation with Stylus Common UI
    • Innovus Implementation System (Block)
    • Innovus Implementation System (Hierarchical)
    • Innovus Low-Power Flow with Stylus Common UI
    • Joules™ Power Calculator
    • Low-Power Flow with Innovus Implementation System (Libraries not included)
    • Low-Power Synthesis Flow with Genus Stylus Common UI
    • Low-Power Synthesis Flow with Genus Synthesis Solution
    • Modus DFT Software Solution
    • Tempus Signoff Timing Analysis and Closure
    • Tempus Signoff Timing Analysis and Closure with Stylus Common UI
    • Test Synthesis Using Genus Synthesis Solution
    • Test Synthesis with Genus Stylus Common UI
    • Virtuoso Digital Implementation
    • Voltus Power Grid Analysis and Signoff with Stylus Common UI
    • Voltus Power-Grid Analysis and Signoff
  • IC Package
    • Allegro Package Designer
    • Allegro Packager Designer Plus
    • Allegro Sigrity PI
    • Allegro Sigrity Package Assessment and Model Extraction
    • Allegro Sigrity Package Assessment and Model Extraction
    • Allegro Sigrity Power-Aware Parallel Bus Analysis
    • Allegro Sigrity SI Foundations
    • Model Generation and Analysis using PowerSI, Broadband SPICE and 3D-EM
    • OrbitIO System Planner
    • SiP Layout
    • SiP Layout
    • Sigrity PowerDC and OptimizePI
    • Sigrity PowerDC and OptimizePI (Français)
    • Sigrity SystemSI for Parallel Bus and Serial Link Analysis
    • TopXplorer SystemSI for Parallel Bus and Serial Link Analysis
  • Languages and Methodologies
    • Behavioral Modeling with VHDL-AMS
    • Behavioral Modeling with Verilog-AMS
    • C++ Language Fundamentals for Design and Verification
    • Essential SystemVerilog for UVM
    • Master VHDL for Verilog Engineers
    • PCB Design at RF - Multi-Gigabit Transmission, EMI Control, and PCB Materials
    • Perl for EDA Engineering
    • Real Modeling with SystemVerilog
    • Real Modeling with Verilog-AMS
    • Specman Advanced Verification
    • Specman Fundamentals for Block-Level Environment Developers
    • SystemC Language Fundamentals
    • SystemC Synthesis with Stratus HLS
    • SystemC Transaction-Level Modeling (TLM 2.0)
    • SystemVerilog Accelerated Verification with UVM
    • SystemVerilog Advanced Register Verification Using UVM
    • SystemVerilog Assertions
    • SystemVerilog Assertions
    • SystemVerilog Real Number Modeling (SV-RNM) Based Advanced Verification
    • SystemVerilog for Design and Verification
    • SystemVerilog for Verification
    • Tcl Scripting for EDA + Intro to Tk
    • Verilog Language and Application
  • PCB Design
    • Advanced Design Verification with the RAVEL Programming Language
    • Advanced PSpice for Power Users
    • Allegro AMS Simulator
    • Allegro AMS Simulator Advanced Analysis
    • Allegro Design Entry HDL Basics
    • Allegro Design Entry HDL Front-to-Back Flow
    • Allegro Design Entry HDL SKILL Programming Language
    • Allegro Design Entry Using OrCAD Capture
    • Allegro Design Entry Using OrCAD Capture
    • Allegro Design Reuse
    • Allegro Design Workbench for Librarians
    • Allegro EDM Administration for OrCAD
    • Allegro EDM Design Entry HDL Front-to-Back Flow
    • Allegro EDM PCB Librarian
    • Allegro EDM for Administrators
    • Allegro EDM for Engineers and Designers
    • Allegro FPGA System Planner
    • Allegro High-Speed Constraint Management
    • Allegro PCB Editor Advanced Methodologies
    • Allegro PCB Editor Basic Techniques
    • Allegro PCB Editor Intermediate Techniques
    • Allegro PCB Editor SKILL Programming Language
    • Allegro PCB Librarian
    • Allegro PCB Router Basics
    • Allegro RF PCB
    • Allegro Sigrity PI
    • Allegro Sigrity Package Assessment and Model Extraction
    • Allegro Sigrity Power-Aware Parallel Bus Analysis
    • Allegro Sigrity SI Foundations
    • Allegro System Architect
    • Allegro System Capture
    • Allegro Team Design Authoring
    • Allegro Tool Setup and Configuration
    • Allegro Update Training
    • Analog Simulation with PSpice
    • Analog Simulation with PSpice Advanced Analysis
    • Celsius Thermal Solver
    • Clarity 3D Solver
    • Essential High-Speed PCB Design for Signal Integrity
    • Model Generation and Analysis using PowerSI, Broadband SPICE and 3D-EM
    • OrCAD CIS
    • OrCAD Capture Constraint Manager PCB Flow
    • OrCAD PCB Editor
    • PCB Design at RF - Multi-Gigabit Transmission, EMI Control, and PCB Materials
    • Sigrity PowerDC and OptimizePI
    • Sigrity PowerDC and OptimizePI (Français)
    • Sigrity SystemSI for Parallel Bus and Serial Link Analysis
    • Simulation Analogique-Mixte PSpice Avancée (Français)
    • TopXplorer SystemSI for Parallel Bus and Serial Link Analysis
  • System Design and Verification
    • C++ Language Fundamentals for Design and Verification
    • Essential SystemVerilog for UVM
    • Foundations of Metric Driven Verification
    • Incisive Functional Safety Simulator
    • Incisive SystemC, VHDL, and Verilog Simulation
    • JasperGold Formal Expert
    • JasperGold Formal Fundamentals
    • Low-Power Simulation with CPF
    • Low-Power Simulation with IEEE Std 1801 UPF
    • Master VHDL for Verilog Engineers
    • Metric Driven Verification Using Cadence vManager
    • Perl for EDA Engineering
    • Perspec System Verifier – Basic
    • Protium Rapid Prototyping Platform
    • SVA, Formal and JasperGold® Fundamentals for Designers
    • Specman Advanced Verification
    • Specman Fundamentals for Block-Level Environment Developers
    • SystemC Language Fundamentals
    • SystemC Synthesis with Stratus HLS
    • SystemC Transaction-Level Modeling (TLM 2.0)
    • SystemVerilog Accelerated Verification with UVM
    • SystemVerilog Advanced Register Verification Using UVM
    • SystemVerilog Assertions
    • SystemVerilog for Design and Verification
    • Tcl Scripting for EDA + Intro to Tk
    • VHDL Language and Application
    • VIP Basic Building Blocks and Usage
    • Verilog Language and Application
    • Verilog for VHDL Users
    • Xcelium Integrated Coverage
    • Xcelium Simulator
    • vManager Tool Usage in Batch Mode
  • Tensilica Processor IP
    • Tensilica Audio Codec API
    • Tensilica ConnX B10 DSP
    • Tensilica ConnX B20 DSP
    • Tensilica ConnX BBE16EP Baseband Engine
    • Tensilica ConnX BBE32EP Baseband Engine
    • Tensilica ConnX BBE64EP Baseband Engine
    • Tensilica DNA 100 Architecture and Programming
    • Tensilica Fusion F1 DSP
    • Tensilica Fusion G3 DSP
    • Tensilica Fusion G6 DSP
    • Tensilica HiFi 2/EP/Mini Audio Engine ISA
    • Tensilica HiFi 3 Audio Engine ISA
    • Tensilica HiFi 4 DSP
    • Tensilica HiFi 5 DSP
    • Tensilica Instruction Extension Language and Design
    • Tensilica System Modeling using XTSC
    • Tensilica Vision P5 DSP
    • Tensilica Vision P6 DSP
    • Tensilica Vision Q7 DSP
    • Tensilica Xtensa Audio Framework
    • Tensilica Xtensa LX Hardware Verification and EDA
    • Tensilica Xtensa LX Processor Fundamentals
    • Tensilica Xtensa LX Processor Interfaces
    • Tensilica Xtensa NX Hardware Verification and EDA
    • Tensilica Xtensa NX Processor Fundamentals
    • Tensilica Xtensa NX Processor Interfaces
    • Tensilica Xtensa Neural Network Compiler v2

CONTACT TRAINING

ONLINE TRAINING
Genus Synthesis Solution v16.1

This online class features the Cadence® Genus™ Synthesis Solution with next generation synthesis capabilities and how SoC design productivity gap is filled by Genus

COURSE DETAILS

NEW COURSE
Mixed-Signal Simulation Using Spectre AMS Designer

GET DETAILS

 
 

A Great Place to Do Great Work!

Sixth year on the FORTUNE 100 list

Our Culture Join The Team
  • 产品
  • 定制 IC /模拟/ RF 设计
  • 数字设计与Signoff
  • IC 封装设计与分析
  • IP
  • PCB 设计与分析
  • 系统分析
  • 系统设计与验证
  • 所有产品
  • 公司
  • 关于我们
  • 管理团队
  • 投资者关系
  • 产业联盟
  • 就业机会
  • Cadence 学术网
  • Supplier
  • 媒体中心
  • Events
  • 新闻中心
  • Cadence 设计
  • 博客
  • 论坛
  • 联系我们
  • 普通咨询
  • 客户支持
  • 媒体中心
  • 全球办公室查找

Stay Connected

Please confirm to enroll for subscription!

Stay Connected

Thank you for subscribing. You will get an email to confirm your subscription.

© 2021 Cadence Design Systems, Inc. All Rights Reserved.

沪ICP备18027754号-2 Terms of Use Privacy US Trademarks
Connect with us