China Public Training Classes Schedule (2018/Q4)
All Courses Learning Map
Cadence Training Services learning maps provide a comprehensive visual overview of the learning opportunities for Cadence customers. They provide recommended course flows as well as tool experience and knowledge levels to guide students through a complete learning plan. Learning Maps cover all Cadence Technologies and reference courses available worldwide.
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Cadence Online Collection Subscriptions
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Custom IC / Analog / RF Design
Circuit Design and Simulation- Analog Modeling and Simulation with SPICE
- Physical Verification System
- Spectre Accelerated Parallel Simulator
- Transistor Level Power Signoff with Voltus-Fi
- Virtuoso ADE Assembler S1: Introducing the Assembler Environment
- Virtuoso ADE Assembler S3: Circuit Checks, Device Asserts, and Reliability Analysis
- Virtuoso ADE Explorer and Assembler S1: ADE Explorer and Single Test Corner Analysis
- Virtuoso ADE Explorer and Assembler S2: ADE Assembler and Multi Test Corner Analysis
- Virtuoso ADE Explorer and Assembler S3: Sweeping Variables and Simulating Corners
- Virtuoso ADE Verifier S1: Setup, Run and View Verification Results
- Virtuoso Analog Design Environment
- Virtuoso Analog Simulation: T2 Creating Sweeps and Running Corner Analysis
- Virtuoso Analog Simulation: T3 Monte Carlo Simulations Using ADEXL
- Virtuoso Analog Simulation: T4 Sensitivity Analysis and circuit Optimization Using ADE(G)XL
- Virtuoso Electrically-Aware Design with Layout-Dependent Effects
- Virtuoso Schematic Editor
- Virtuoso System Design Platform
- Virtuoso Visualization and Analysis
Circuit Modeling- Analog Modeling with Verilog-A
- Behavioral Modeling with VHDL-AMS
- Behavioral Modeling with Verilog-AMS
- Command-Line Based Mixed-Signal Simulations with the Xcelium Use Model
- Mixed Signal Simulations Using AMS Designer
- Mixed Signal Simulations Using Spectre AMS Designer/Xcelium Simulator
- Real Modeling with SystemVerilog
Circuit Simulation- Command-Line Based Mixed-Signal Simulations with the Xcelium Use Model
- Mixed Signal Simulations Using AMS Designer
- Mixed Signal Simulations Using Spectre AMS Designer/Xcelium Simulator
- Simulation and Analysis Using OCEAN
- Spectre Accelerated Parallel Simulator
- Spectre Simulations Using Virtuoso ADE
- Spectre Simulator Fundamentals S1: Spectre Basics
- Spectre Simulator Fundamentals S2: Large-Signal Analyses
- Spectre Simulator Fundamentals S3: Small-Signal Analyses
- Spectre Simulator Fundamentals S4: Measurement Description Language
- Virtuoso AMS Designer
- Virtuoso Analog Simulation: T2 Creating Sweeps and Running Corner Analysis
- Virtuoso Analog Simulation: T3 Monte Carlo Simulations Using ADEXL
- Virtuoso Analog Simulation: T4 Sensitivity Analysis and circuit Optimization Using ADE(G)XL
- Virtuoso Spectre Pro S1: DC Algorithm
- Virtuoso Spectre Pro S2: AC, XF, STB, and Noise Analyses
- Virtuoso Spectre Pro S3: Transient Algorithm
- Virtuoso Spectre Pro S4: Measuring Accurate Fourier Transforms
- Virtuoso Spectre Pro S5: Transient Noise
- Virtuoso UltraSim Full-chip Simulator
Layout Verification- Assura Parasitic Extraction (RCX)
- Assura RCX Developer
- Assura Rules Writer
- Assura Verification
- Cadence QRC Techgen Developer
- MaskCompose Automated Reticle Design Synthesis
- Pegasus Verification System
- Physical Verification Language Rules Writer
- Physical Verification System
- Quantus Transistor-Level T1: Overview and Technology Setup
- Quantus Transistor-Level T2: Parasitic Extraction
- Quantus Transistor-Level T3: Extracted View Flows and Advanced Features
Physical Design- Using Virtuoso Constraints Effectively
- Virtuoso Connectivity-Driven Layout Transition
- Virtuoso Floorplanner
- Virtuoso Layout Pro: T1 Environment and Basic Commands (L)
- Virtuoso Layout Pro: T3 Basic Commands (XL)
- Virtuoso Layout Pro: T4 Advanced Commands (XL)
- Virtuoso Layout Pro: T7 Module Generator and Floorplanner (XL/GXL)
- Virtuoso Layout Pro: T8 Debugging Layout Issues
- Virtuoso Space-based Router
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Digital Design and Signoff
Implementation- Innovus Clock Concurrent Optimization Technology for Clock Tree Synthesis
- Innovus Clock Concurrent Optimization Technology with Stylus Common UI
- Innovus Implementation System (Block)
- Innovus Implementation System (Hierarchical)
- Low-Power Flow with Innovus Implementation System
- Virtuoso Digital Implementation
Synthesis and Test- Advanced Synthesis with Genus Synthesis Solution
- Fundamentals of IEEE 1801 Low-Power Specification Format
- Genus Synthesis Solution
- Joules™ Power Calculator
- Low-Power Synthesis Flow with Genus Synthesis Solution
- Modus DFT Software Solution
- Test Synthesis Using Genus Synthesis Solution
- Test Synthesis with Genus Stylus Common UI
- Virtuoso Digital Implementation
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IC Package Design and Analysis
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Languages and Methodologies
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PCB Design and Analysis
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System Design and Verification
SELF PACED ONLINE TRAINING
Online Training Subscription
Multiple online courses of one or more technology groups, for 12 months unlimited, per student
ONLINE TRAINING
Genus Synthesis Solution v16.1
This online class features the Cadence® Genus™ Synthesis Solution with next generation synthesis capabilities and how SoC design productivity gap is filled by Genus