Overview

Best-in-class eUSB Verification IP for your IP, SoC, and system-level design testing.

The Cadence® Verification IP (VIP) for eUSB is a complete VIP solution for the Embedded USB2 (eUSB2) Physical Layer Supplement to the USB Revision 2.0 Specification, Revision 1.1. It provides a mature and comprehensive verification IP (VIP) for the eUSB protocol. Incorporating the latest protocol updates, the eUSB2 VIP is not only just a complete bus functional model (BFM) for the DUT operating in eUSB Native Mode but it also provides integrated automatic protocol checks and coverage model.

This VIP for eUSB provides support for any eUSB device in native mode: Host(eDSPn) or Device(eUSPn), in Repeater Mode: Host(eDSPr) or Device(eUSPr), Host Repeater, Peripheral Repeater and Hybrid Repeater. . It supports all eUSB operational speeds: Low, Full, or High. It provides multiple signaling eUSB interfaces: single-ended signaling for low-/full-speed mode and low-voltage differential signaling for high-speed mode to test and monitor all possible configurations of USB devices. The eUSB VIP is designed in such a way that it is easy for you to integrate in testbenches for IP, System-on-chip (SOC) and system level. The eUSB VIP helps you to reduce time to test by accelerate verification closure and ensure end product quality.

The VIP for USB runs on all major simulators and supports all main verification languages such as Verilog, System Verilog and e alongside with industry-standard methodologies for Testbench writing such as Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

Supported specifications: eUSB2 2.0, eUSB2 1.0 and USB 1.1.

eUSB diagram1
eUSB diagram 2

Product Highlights

  • Support testbench languages for SystemVerilog, UVM, OVM, and e
  • Runs on all major simulators
  • Generation of constraint-random bus traffic
  • Verify all device types: Host(eDSPn) or Device(eUSPn), Repeater Mode: Host(eDSPr) or Device(eUSPr), DUT as Hybrid Repeater.
  • Dynamic activation and reconfigure the VIP attributes anytime during the simulation
  • Built-in verification plan, protocol checks and coverage model
  • Callback access at multiple TX and RX queue points for scoreboarding and data manipulation

Key Features

The following table describes key features from the specifications that are implemented in the VIP:

Feature Name

Description

Supported DUT Types
  • All eUSB DUT types such as in native mode: Host(eDSPn) or Device(eUSPn), in Repeater Mode: Host(eDSPr) or Device(eUSPr), Host Repeater, Peripheral Repeater and Hybrid Repeater.

Transaction Types
  • All types of transfers: bulk, control, interrupt, and isochronous transactions

Backward Compatible
  • Backward compatibility with USB 1.1 specifications

Enumeration
  • Provides a complete USB protocol hierarchy enumeration process for host and device models

Operational Speed
  • Operates at high, full, or low speed

Reset Signaling
  • Supports low/full-speed reset and high-speed chirp handshake

Suspend/Resume
  • Supports suspend, resume, remote wake-up, and low-power management (LPM)

Transaction and Packet Checks
  • Checks for all transaction and packet rules including inter-packet gap and propagation delays

Protocol Features in Repeater mode
  • Support for Glitch Handling
  • Support for Variable SYNC bits handling
  • Support for first distorted SYNC bit handling
  • Support for Dribble Handling
  • Support for SE1 skew handling
  • Support for port reset in all states

Translator
  • Digital translator available for sending eUSB-compliant traffic

Register interface
  • Support to change the severity (Error, Warning, Info) of the protocol assertions
  • Support to initiate various commands such as reset, suspend/resume/remote wake-up, disconnect/connect, and so on
  • Support to control the functionality such as end-point buffers, chirp sequence, and clock frequency
  • Support to store information of the VIP model such as, device states, device address, end-point information, and other information that is easily accessible by the testbench
  • Support to insert error injections at the eUSB Phy
  • Support to initiate go to Port Reset from any state, issue silent and soft disconnect by device (eUSPn)

Predefined Error Injections
  • Device drives Port Reset during POR
  • Host drive ED+ as 1 instead of driving SE1 in Port Reset
  • Device corrupts the ACK in Port Configuration
  • Device drives invalid Connect Signal depending on the speed of operation
  • Device drives invalid ping
  • Host does not send an EOP
  • Host drives J signal instead of K during the resume operation
  • Host does not drive Resume signal after Remote wakeup from device
  • Host sends corrupted EOP to the device

仿真测试套件

广泛的测试集合、覆盖率模型和验证计划，与规范有明确的联系，可进行简单而快速的符合性测试。

TripleCheck Test Suite

掌握您的工具

教程、文件和当地专家

Cadence 在线支持

通过在线培训、VIP门户、应用笔记和故障排除文章提高您使用Cadence验证IP的效率

了解更多
Related Products
System VIP

Cadence® System-Level Verification IP (System VIP) takes Cadence’s market leadership in IP-level verification automation and brings it to the chip level. It consists of a suite of tools and libraries, each working seamlessly with Cadence’s simulation, emulation, and prototyping engines.

Learn More
Design IP

Silicon-proven Advanced Memory interface IP and industry-leading PCIe and High Speed SerDes IP in leading edge foundry processes

Learn More
Xcelium Logic Simulation

Cadence® Xcelium™ Logic Simulation provides best-in-class core engine performance for SystemVerilog, VHDL, SystemC®, e, UVM, mixed signal, low power, and X-propagation. It leverages single-core and multi-core simulation technology for best individual test performance and machine learning-optimized regression technology for the best regression throughput.

Learn More
Palladium Emulation

Cadence® Palladium® emulation platform provides early software development, hardware/software verification and debug, and in circuit emulation. It provides the highest debug productivity early in the design cycle when the RTL is still changing.

Learn More